Fixed a problem in F4 clock DCKCFGR initialization.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12551 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2019-01-19 09:44:41 +00:00
parent dd2092cec6
commit 675ee683d0
5 changed files with 5 additions and 29 deletions

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@ -33,7 +33,7 @@
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@ -34,13 +34,13 @@ static THD_FUNCTION(Thread1, arg) {
palSetLine(LINE_LED2); palSetLine(LINE_LED2);
chThdSleepMilliseconds(50); chThdSleepMilliseconds(50);
palSetLine(LINE_LED3); palSetLine(LINE_LED3);
chThdSleepMilliseconds(200); chThdSleepMilliseconds(150);
palClearLine(LINE_LED1); palClearLine(LINE_LED1);
chThdSleepMilliseconds(50); chThdSleepMilliseconds(50);
palClearLine(LINE_LED2); palClearLine(LINE_LED2);
chThdSleepMilliseconds(50); chThdSleepMilliseconds(50);
palClearLine(LINE_LED3); palClearLine(LINE_LED3);
chThdSleepMilliseconds(200); chThdSleepMilliseconds(150);
} }
} }

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@ -288,12 +288,10 @@ void stm32_clock_init(void) {
#endif #endif
#if !defined(STM32F413xx) #if !defined(STM32F413xx)
RCC->DCKCFGR = dckcfgr | RCC->DCKCFGR = dckcfgr |
STM32_TIMPRE | STM32_PLLSAIDIVR | STM32_TIMPRE | STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;
STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;
#else #else
RCC->DCKCFGR = dckcfgr | RCC->DCKCFGR = dckcfgr |
STM32_TIMPRE | STM32_TIMPRE | STM32_PLLDIVR | STM32_PLLI2SDIVR;
STM32_PLLDIVR | STM32_PLLI2SDIVR;
#endif #endif
} }
#endif #endif

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@ -204,40 +204,20 @@
* @brief Clock of timers connected to APB1 * @brief Clock of timers connected to APB1
* (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14). * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
*/ */
#if !defined(STM32F446xx) || defined(__DOXYGEN__)
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1) #define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#else #else
#define STM32_TIMCLK1 (STM32_PCLK1 * 2) #define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#endif #endif
#else /* defined(STM32F446xx) */
#if STM32_PPRE1 == STM32_PPRE1_DIV1
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
#endif
#endif /* defined(STM32F446xx) */
/** /**
* @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11). * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
*/ */
#if !defined(STM32F446xx) || defined(__DOXYGEN__)
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1) #define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#else #else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2) #define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#endif #endif
#else /* defined(STM32F446xx) */
#if STM32_PPRE2 == STM32_PPRE2_DIV1
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
#endif
#endif /* defined(STM32F446xx) */
#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */ #else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \ #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \

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@ -196,8 +196,6 @@
- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1). - EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1). - EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1). - EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
- HAL: Fixed invalid timer frequency calculation for STM32F446 (bug #1002)
(backported to 18.2.2 and 17.6.5).
- HAL: Fixed invalid checks in STM32H7 HAL (bug #1000) - HAL: Fixed invalid checks in STM32H7 HAL (bug #1000)
(backported to 18.2.2). (backported to 18.2.2).
- OTH: Fixed problem in STM32H743 GCC linker file (bug #998) - OTH: Fixed problem in STM32H743 GCC linker file (bug #998)