diff --git a/os/hal/ports/AVR/MEGA/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/AVR/MEGA/LLD/ADCv1/hal_adc_lld.c index 3671fe002..ef7639451 100644 --- a/os/hal/ports/AVR/MEGA/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/ADCv1/hal_adc_lld.c @@ -68,7 +68,7 @@ static size_t getAdcChannelNumberFromMask(uint8_t mask, mask >>= 1; } - /* error, should never reach this line */ + /* Error, should never reach this line */ return -1; } @@ -109,7 +109,7 @@ OSAL_IRQ_HANDLER(ADC_vect) { _adc_isr_full_code(&ADCD1); } else { - setAdcChannel(getAdcChannelNumberFromMask(ADCD1.grpp->channelsMask,currentChannel)); + setAdcChannel(getAdcChannelNumberFromMask(ADCD1.grpp->channelsMask, currentChannel)); ADCSRA |= 1 << ADSC; } @@ -132,7 +132,7 @@ void adc_lld_init(void) { /* Prescaler 128, only value possible at 20Mhz, interrupt. */ ADCSRA = (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0) | (1 << ADIE); - /* uso aref, only valid for arduino. arduino ha aref collegato. */ + /* Uso aref, only valid for arduino. arduino ha aref collegato. */ ADMUX = (0 << REFS1) | (0 << REFS0); } @@ -179,9 +179,9 @@ void adc_lld_stop(ADCDriver *adcp) { */ void adc_lld_start_conversion(ADCDriver *adcp) { - adcp->currentBufferPosition=0; + adcp->currentBufferPosition = 0; - setAdcChannel(getAdcChannelNumberFromMask(adcp->grpp->channelsMask,0)); + setAdcChannel(getAdcChannelNumberFromMask(adcp->grpp->channelsMask, 0)); ADCSRA |= 1 << ADSC; } diff --git a/os/hal/ports/AVR/MEGA/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/AVR/MEGA/LLD/GPIOv1/hal_pal_lld.h index b33bd150d..63743b395 100644 --- a/os/hal/ports/AVR/MEGA/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/AVR/MEGA/LLD/GPIOv1/hal_pal_lld.h @@ -15,8 +15,8 @@ */ /** - * @file GPIOv1/hal_pal_lld.h - * @brief AVR/MEGA PAL subsystem low level driver header. + * @file GPIOv1/hal_pal_lld.h + * @brief AVR/MEGA PAL subsystem low level driver header. * * @addtogroup PAL * @{ @@ -59,7 +59,7 @@ * @brief Forms a line identifier. * @details A port/pad pair are encoded into an @p ioline_t type. The encoding * of this type is platform-dependent. - * @note In this driver the pad number and the port identifier are + * @note In this driver the pad number and the port identifier are * encoded in a structure of type ioline_t. */ #define PAL_LINE(port, pad) _pal_lld_setlineid(port, pad) @@ -172,7 +172,7 @@ typedef uint8_t iopadid_t; typedef struct { ioportid_t port; /* Line port identifier. */ iopadid_t pad; /* Line pad identifier. */ -}ioline_t; +} ioline_t; /** * @brief Type of an event mode. @@ -276,7 +276,7 @@ typedef uint8_t ioeventmode_t; /*==========================================================================*/ /* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in hal_pal_lld.c. */ +/* Functions, if so please put them in hal_pal_lld.c. */ /*==========================================================================*/ /** diff --git a/os/hal/ports/AVR/MEGA/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/AVR/MEGA/LLD/I2Cv1/hal_i2c_lld.c index 02709291f..c3e5c93c7 100644 --- a/os/hal/ports/AVR/MEGA/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/I2Cv1/hal_i2c_lld.c @@ -197,7 +197,7 @@ void i2c_lld_stop(I2CDriver *i2cp) { * @param[in] timeout the number of ticks before the operation timeouts, * the following special values are allowed: * - @a TIME_INFINITE no timeout - * + * * @return The operation status. * @retval MSG_OK if the function succeeded. * @retval MSG_RESET if one or more I2C errors occurred, the errors can @@ -239,7 +239,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, * @param[in] timeout the number of ticks before the operation timeouts, * the following special values are allowed: * - @a TIME_INFINITE no timeout - * + * * @return The operation status. * @retval MSG_OK if the function succeeded. * @retval MSG_RESET if one or more I2C errors occurred, the errors can diff --git a/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.c index 33ad1cffa..3c4872559 100644 --- a/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.c @@ -129,9 +129,9 @@ void spi_lld_start(SPIDriver *spip) { if (&SPID1 == spip) { /* Configures the peripheral. */ /* Note that some bits are forced: - SPI interrupt disabled, - SPI enabled, - SPI master enabled. */ + SPI interrupt disabled, + SPI enabled, + SPI master enabled. */ SPCR = (spip->config->spcr & ~(SPI_CR_SPIE)) | SPI_CR_MSTR | SPI_CR_SPE; SPSR = spip->config->spsr; @@ -206,7 +206,6 @@ void spi_lld_unselect(SPIDriver *spip) { } - /** * @brief Exchanges data on the SPI bus. * @details This asynchronous function starts a simultaneous transmit/receive @@ -269,11 +268,11 @@ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { SPCR &= ~(SPI_CR_SPIE); SPDR = frame >> 8; - while (!(SPSR & SPI_SR_SPIF)) ; + while (!(SPSR & SPI_SR_SPIF)); spdr = SPDR << 8; SPDR = frame & 0xFF; - while (!(SPSR & SPI_SR_SPIF)) ; + while (!(SPSR & SPI_SR_SPIF)); spdr |= SPDR; dummy = SPSR; @@ -294,7 +293,7 @@ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) { SPCR &= ~(SPI_CR_SPIE); SPDR = frame; - while (!(SPSR & SPI_SR_SPIF)) ; + while (!(SPSR & SPI_SR_SPIF)); spdr = SPDR; dummy = SPSR; diff --git a/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.h b/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.h index 8c712ff6e..ce9a1cd39 100644 --- a/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.h +++ b/os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.h @@ -112,7 +112,6 @@ size_t exbytes; \ size_t exidx; - /** * @brief Low level fields of the SPI configuration structure. */ diff --git a/os/hal/ports/AVR/MEGA/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/AVR/MEGA/LLD/SYSTICKv1/hal_st_lld.c index 0366a4a76..7283ab09b 100644 --- a/os/hal/ports/AVR/MEGA/LLD/SYSTICKv1/hal_st_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/SYSTICKv1/hal_st_lld.c @@ -193,11 +193,11 @@ void st_lld_init(void) { TCCR1A = 0; TCCR1B = _BV(WGM12); - /* start disabled. */ + /* Start disabled. */ TCCR1C = 0; OCR1A = 0; TCNT1 = 0; - TIFR_REG = _BV(OCF1A); /* Reset pending. */ + TIFR_REG = _BV(OCF1A); /* Reset pending. */ TIMSK_REG = 0; TCCR1B = PRESCALER; diff --git a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_gpt_lld.c b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_gpt_lld.c index f4d0c5534..19d79d114 100644 --- a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_gpt_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_gpt_lld.c @@ -93,9 +93,12 @@ GPTDriver GPTD5; /*==========================================================================*/ static uint16_t ratio_base[] = { 1024, 256, 64, 8, 1 }; -static uint8_t clock_source_base[]= { 5, 4, 3, 2, 1 }; -//static uint16_t ratio_extended[] = { 1024, 256, 128, 64, 32, 8, 1 }; -//static uint8_t clock_source_extended[] = { 7, 6, 5, 4, 3, 2, 1 }; +static uint8_t clock_source_base[] = { 5, 4, 3, 2, 1 }; + +/* Extended tables. + * static uint16_t ratio_extended[] = { 1024, 256, 128, 64, 32, 8, 1 }; + * static uint8_t clock_source_extended[] = { 7, 6, 5, 4, 3, 2, 1 }; + */ /*==========================================================================*/ /* Driver local functions. */ @@ -334,7 +337,7 @@ void gpt_lld_start(GPTDriver *gptp) { */ void gpt_lld_stop(GPTDriver *gptp) { - /* nothing to be done */ + /* Nothing to be done */ if (gptp->state == GPT_READY) { /* Clock de-activation.*/ } @@ -393,7 +396,7 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { gptp->callback = gpt_lld_dummy_callback; gpt_lld_start_timer(gptp, interval); - //FIX + /* FIX */ while (gptp->state != GPT_READY) {} } diff --git a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.c b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.c index 0c4ccd40f..155b5e0c6 100644 --- a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.c @@ -40,7 +40,7 @@ typedef struct { volatile uint8_t *timsk; } icu_registers_t; -static icu_registers_t regs_table[]= +static icu_registers_t regs_table[] = { #if AVR_ICU_USE_TIM1 || defined(__DOXYGEN__) {&TCCR1A, &TCCR1B, &TCNT1, &TIMSK1}, diff --git a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.h b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.h index 9bdbdee6c..457601f85 100644 --- a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.h +++ b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.h @@ -157,7 +157,6 @@ struct ICUDriver { /* Driver macros. */ /*==========================================================================*/ - /** * @brief Returns the width of the latest pulse. * @details The pulse width is defined as number of ticks between the start diff --git a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_pwm_lld.c b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_pwm_lld.c index 291c2f416..c0429242a 100644 --- a/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_pwm_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_pwm_lld.c @@ -53,7 +53,7 @@ typedef struct { volatile uint16_t *icr; } timer_registers_t; -static timer_registers_t regs_table[]= +static timer_registers_t regs_table[] = { #if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__) #if defined(OCR1C) @@ -369,7 +369,7 @@ void pwm_lld_start(PWMDriver *pwmp) { 1, to keep compatibility with old code. */ const uint8_t log_ratio_timer2[] = {0, 3, 5, 6, 7, 8, 10}; uint8_t n; - for (n=0; nconfig->frequency == (F_CPU >> log_ratio_timer2[n])) { cs_value = n + 1; break; @@ -395,7 +395,7 @@ void pwm_lld_start(PWMDriver *pwmp) { keep compatibility with old code. */ const uint8_t log_ratio_timer1[] = {0, 3, 6, 8, 10}; uint8_t n; - for (n=0; nconfig->frequency == (F_CPU >> log_ratio_timer1[n])) { cs_value = n + 1; break; diff --git a/os/hal/ports/AVR/MEGA/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/AVR/MEGA/LLD/USARTv1/hal_serial_lld.c index f88c5dd00..95a758c06 100644 --- a/os/hal/ports/AVR/MEGA/LLD/USARTv1/hal_serial_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/USARTv1/hal_serial_lld.c @@ -50,7 +50,7 @@ SerialDriver SD1; #define AVR_SD1_TX_VECT USART0_UDRE_vect #else #error "Cannot find USART to use for SD1" - #endif + #endif #endif /* AVR_SERIAL_USE_USART0 */ /** @@ -160,7 +160,7 @@ static void usart0_init(const SerialConfig *config) { default: ucsr0c = (1 << UCSZ00) | (1 << UCSZ01); } - + #if defined(__AVR_ATmega162__) UCSR0C = (1 << URSEL0) | ucsr0c; #else @@ -205,7 +205,7 @@ static void usart1_init(const SerialConfig *config) { UCSR1B = (1 << RXEN1) | (1 << TXEN1) | (1 << RXCIE1); switch (config->sc_bits_per_char) { case USART_CHAR_SIZE_5: - ucsr1c = 0; + ucsr1c = 0; break; case USART_CHAR_SIZE_6: ucsr1c = (1 << UCSZ10); @@ -221,7 +221,7 @@ static void usart1_init(const SerialConfig *config) { default: ucsr1c = (1 << UCSZ10) | (1 << UCSZ11); } - + #if defined(__AVR_ATmega162__) UCSR1C = (1 << URSEL1) | ucsr1c; #else diff --git a/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.c index 4a976c75a..e83555163 100644 --- a/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.c @@ -249,7 +249,7 @@ static void usb_fifo_write(USBDriver *usbp, usbep_t ep, size_t n) { if (n > epcp->in_maxsize) n = epcp->in_maxsize; - /* i is number of bytes remaining to transmit minus 1 (to handle 256b case). */ + /* I is number of bytes remaining to transmit minus 1 (to handle 256b case). */ uint8_t i = n - 1; /* Must lock for entire operation to ensure nothing changes the ENUM value. */ @@ -271,7 +271,7 @@ static void usb_fifo_read(USBDriver *usbp, usbep_t ep, size_t n) { return; if (n > epcp->out_maxsize) n = epcp->out_maxsize; - /* i is number of bytes remaining to receive minus 1 (to handle 256b case). */ + /* I is number of bytes remaining to receive minus 1 (to handle 256b case). */ uint8_t i = n - 1; /* Must lock for entire operation to ensure nothing changes the ENUM value. */ @@ -426,7 +426,7 @@ void usb_lld_start(USBDriver *usbp) { /* Reset and disable all endpoints. */ UERST = 0x7f; UERST = 0; - for (i = 0; i < USB_MAX_ENDPOINTS; ++i){ + for (i = 0; i < USB_MAX_ENDPOINTS; ++i) { UENUM = i; UEIENX = 0; UEINTX = 0; diff --git a/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.h b/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.h index 54f4547ce..5d9234685 100644 --- a/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.h +++ b/os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.h @@ -368,7 +368,7 @@ struct USBDriver { * @notapi */ #define usb_lld_wakeup_host(usbp) \ - do{ \ + do { \ } while (true) /*==========================================================================*/ diff --git a/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.c index 704f459c9..06364dc06 100644 --- a/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.c @@ -189,7 +189,6 @@ void _pal_lld_enablepadevent(ioportid_t port, #else #error The selected port dont have an EXT INTx pin. */ - //} } /** diff --git a/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.h index a040ac1a6..311aae5b0 100644 --- a/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.h @@ -15,8 +15,8 @@ */ /** - * @file GPIOv1/hal_pal_lld.h - * @brief AVR Tiny GPIO low level driver header file. + * @file GPIOv1/hal_pal_lld.h + * @brief AVR Tiny GPIO low level driver header file. * * @addtogroup PAL * @{ @@ -59,7 +59,7 @@ * @brief Forms a line identifier. * @details A port/pad pair are encoded into an @p ioline_t type. The encoding * of this type is platform-dependent. - * @note In this driver the pad number and the port identifier are + * @note In this driver the pad number and the port identifier are * encoded in a structure of type ioline_t. */ #define PAL_LINE(port, pad) _pal_lld_setlineid(port, pad) @@ -172,7 +172,7 @@ typedef uint8_t iopadid_t; typedef struct { ioportid_t port; /* Line port identifier. */ iopadid_t pad; /* Line pad identifier. */ -}ioline_t; +} ioline_t; /** * @brief Type of an event mode. @@ -276,7 +276,7 @@ typedef uint8_t ioeventmode_t; /*===========================================================================*/ /* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in hal_pal_lld.c. */ +/* Functions, if so please put them in hal_pal_lld.c. */ /*===========================================================================*/ /** diff --git a/os/hal/ports/AVR/TINY/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/AVR/TINY/LLD/SYSTICKv1/hal_st_lld.h index 4a2ff5eff..60f3f54bc 100644 --- a/os/hal/ports/AVR/TINY/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/AVR/TINY/LLD/SYSTICKv1/hal_st_lld.h @@ -106,7 +106,7 @@ static inline void st_lld_start_alarm(systime_t time) { /* Reset pending. */ TIFR_REG = _BV(OCF1A); - /* enable interrupt */ + /* Enable interrupt */ TIMSK_REG = _BV(OCIE1A); } diff --git a/os/hal/ports/AVR/TINY/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/AVR/TINY/LLD/USARTv1/hal_uart_lld.c index 14cfc5bc5..0cdbf83f3 100644 --- a/os/hal/ports/AVR/TINY/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/AVR/TINY/LLD/USARTv1/hal_uart_lld.c @@ -39,12 +39,12 @@ /* Driver exported variables. */ /*==========================================================================*/ -/** @brief USART1 UART driver identifier.*/ +/** @brief USART1 UART driver identifier. */ #if AVR_UART_USE_USART1 || defined(__DOXYGEN__) UARTDriver UARTD1; #endif -/** @brief USART2 UART driver identifier.*/ +/** @brief USART2 UART driver identifier. */ #if AVR_UART_USE_USART2 || defined(__DOXYGEN__) UARTDriver UARTD2; #endif @@ -78,7 +78,7 @@ static void usart_stop(UARTDriver *uartp) { */ static void usart_start(UARTDriver *uartp) { - /* Defensive programming, starting from a clean state.*/ + /* Defensive programming, starting from a clean state. */ usart_stop(uartp); #if AVR_UART_USE_USART1 @@ -192,10 +192,10 @@ void uart_lld_stop(UARTDriver *uartp) { * @notapi */ void uart_lld_start_send(UARTDriver *uartp, size_t n, const uint8_t *txbuf) { - + #if AVR_UART_USE_USART1 if (&UARTD1 == uartp) { - /* Starting transfer.*/ + /* Starting transfer. */ while (n--) { while (LINSIR & (1 << LBUSY)); LINDAT = *txbuf; @@ -218,7 +218,7 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const uint8_t *txbuf) { */ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - /* Stopping previous activity (idle state).*/ + /* Stopping previous activity (idle state). */ /* TODO: Implement this function. */ } diff --git a/os/hal/ports/AVR/XMEGA/ATXMEGAxxxA4U/hal_lld.c b/os/hal/ports/AVR/XMEGA/ATXMEGAxxxA4U/hal_lld.c index a0e5688a2..737bb07fb 100644 --- a/os/hal/ports/AVR/XMEGA/ATXMEGAxxxA4U/hal_lld.c +++ b/os/hal/ports/AVR/XMEGA/ATXMEGAxxxA4U/hal_lld.c @@ -52,10 +52,10 @@ void hal_lld_init(void) { OSC_CTRL |= OSC_RC32MEN_bm; /* Setup 32Mhz crystal. */ - + while(!(OSC_STATUS & OSC_RC32MRDY_bm)); /* Wait the systeme clock to stabilize. */ - + CCP = CCP_IOREG_gc; /* Trigger protection mechanism. */ CLK_CTRL = CLK_SCLKSEL_RC32M_gc; /* Enable internal 32Mhz crystal.*/ } diff --git a/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.c b/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.c index cf1931a66..23029677a 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.c @@ -196,7 +196,7 @@ cryerror_t cry_lld_aes_loadkey(CRYDriver *cryp, (void)cryp; if (size != AES_BLOCK_SIZE) { - return CRY_ERR_INV_KEY_SIZE; /* invalid size error code. */ + return CRY_ERR_INV_KEY_SIZE; /* Invalid size error code. */ } /* Load the Key into the AES key memory. */ @@ -249,14 +249,14 @@ cryerror_t cry_lld_encrypt_AES(CRYDriver *cryp, aes_lld_start(); /* Wait the Encryption to finish or an error to occurs. */ - do{ + do { } while ((AES.STATUS & (AES_SRIF_bm|AES_ERROR_bm)) == 0); /* Check error. */ - if((AES.STATUS & AES_ERROR_bm) == 0) { + if ((AES.STATUS & AES_ERROR_bm) == 0) { /* Store the result of the encryption. */ - for(i = 0; i < AES_BLOCK_SIZE; i++) { + for (i = 0; i < AES_BLOCK_SIZE; i++) { dest[i] = AES.STATE; } } diff --git a/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.h b/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.h index 8143834b1..a8a114075 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.h +++ b/os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.h @@ -55,7 +55,7 @@ /** * @brief Size of one block data, always 128-bits (16 bytes). */ -#define AES_BLOCK_SIZE 16 +#define AES_BLOCK_SIZE 16 /*==========================================================================*/ /* Driver pre-compile time settings. */ @@ -65,6 +65,7 @@ * @name AVR configuration options * @{ */ + /** * @brief CRY1 driver enable switch. * @details If set to @p TRUE the support for CRY1 is included. @@ -98,8 +99,8 @@ typedef struct CRYDriver CRYDriver; * @note It could be empty on some architectures. */ typedef struct { - bool autof; // Auto start feature - bool xorf; // XOR feature + bool autof; /* Auto start feature. */ + bool xorf; /* XOR feature. */ } CRYConfig; /** diff --git a/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.c b/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.c index 2138df78c..e13671c10 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.c @@ -70,10 +70,10 @@ DACDriver DACD1; */ static bool dac_is_channel_data_empty(DACDriver *dacp) { - bool dacStatus = (dacp->dacblock->STATUS & + bool dacStatus = (dacp->dacblock->STATUS & (dacp->config->ch ? DAC_CH1DRE_bm : DAC_CH0DRE_bm)); - return dacStatus; + return dacStatus; } /** @@ -110,9 +110,9 @@ static void dac_set_trigger_mode(DACDriver *dacp) { static void dac_set_operation_mode(DACDriver *dacp) { if (dacp->config->om == DAC_OPMODE_SINGLE) - dacp->dacblock->CTRLB = (dacp->dacblock->CTRLB & ~DAC_CHSEL_gm ) | DAC_CHSEL_SINGLE_gc; + dacp->dacblock->CTRLB = (dacp->dacblock->CTRLB & ~DAC_CHSEL_gm) | DAC_CHSEL_SINGLE_gc; else - dacp->dacblock->CTRLB = (dacp->dacblock->CTRLB & ~DAC_CHSEL_gm ) | DAC_CHSEL_DUAL_gc; + dacp->dacblock->CTRLB = (dacp->dacblock->CTRLB & ~DAC_CHSEL_gm) | DAC_CHSEL_DUAL_gc; } /** @@ -123,7 +123,7 @@ static void dac_set_operation_mode(DACDriver *dacp) { */ static void dac_set_ajusted_mode(DACDriver *dacp) { - dacp->dacblock->CTRLC = (dacp->dacblock->CTRLC & ~(DAC_LEFTADJ_bm)) | + dacp->dacblock->CTRLC = (dacp->dacblock->CTRLC & ~(DAC_LEFTADJ_bm)) | (dacp->config->da ? DAC_LEFTADJ_bm : 0x00); } diff --git a/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.h b/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.h index 9572ac4d4..281321458 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.h +++ b/os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.h @@ -181,7 +181,7 @@ typedef struct { */ typedef struct { dacchan_t ch; /* DAC channel id. */ - dactrigmode_t tm; /* register write/event trigger. */ + dactrigmode_t tm; /* Register write/event trigger. */ dacopmode_t om; /* DAC operation mode. */ dacajustmode_t da; /* DAC (left/rigth) ajustement. */ dacrefsel_t vr; /* DAC voltage reference. */ diff --git a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c index 8c4a08840..25c885688 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c @@ -88,28 +88,6 @@ OSAL_IRQ_HANDLER(DMA_CH3_vect) { /* Driver exported functions. */ /*==========================================================================*/ - - -// Optional reload of source and destination addresses at the end of each: -// - Burst -// - Block -// - Tansaction - -// Optional interrupt at the end of transaction - -// Optional connection to CRC generator for CRC on DMA data - -// void dma_lld_set_transfer_src() /* source. */ -// void dma_lld_set_transfer_dst() /* Destination. */ -// void dma_lld_set_transfer_trg() /* Trigger. */ -// void dma_lld_set_transfer_siz() /* Size. (1, 2, 4 or 8). */ - -// void dma_lld_read() -// void dma_lld_write() -// void isr_on_transfer_complate() -// void dma_lld_set_double_buffer_mode() -// void isr_on_error_during_tranfer() - /** * @brief Enable DMA controller. * @@ -174,12 +152,12 @@ void dmaChannelReset(DMA_CH_t *dmacp) { } -void dmaEnableSingleShot(DMA_CH_t * dmacp ) { +void dmaEnableSingleShot(DMA_CH_t * dmacp) { dmacp->CTRLA |= DMA_CH_SINGLE_bm; } -void dmaDisableSingleShot(DMA_CH_t * dmacp ) { +void dmaDisableSingleShot(DMA_CH_t * dmacp) { dmacp->CTRLA &= ~DMA_CH_SINGLE_bm; } diff --git a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h index 01910026e..928ed0d50 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h +++ b/os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h @@ -41,7 +41,6 @@ /* Driver data structures and types. */ /*==========================================================================*/ - /** * @brief Programmable channel priority */ diff --git a/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.c index d5ebcfec8..c2298f0d4 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.c @@ -189,7 +189,6 @@ void _pal_lld_enablepadevent(ioportid_t port, #else #error The selected port dont have an EXT INTx pin. */ - //} } /** diff --git a/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.h index d2a24599b..70e5c337f 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.h @@ -170,7 +170,7 @@ typedef uint8_t iopadid_t; typedef struct { ioportid_t port; /* Line port identifier. */ iopadid_t pad; /* Line pad identifier. */ -}ioline_t; +} ioline_t; /** * @brief Type of an event mode. @@ -260,7 +260,7 @@ typedef uint8_t ioeventmode_t; /*==========================================================================*/ /* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in hal_pal_lld.c. */ +/* Functions, if so please put them in hal_pal_lld.c. */ /*==========================================================================*/ /** diff --git a/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.c index 75c0505e7..67b8c2bec 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.c @@ -57,54 +57,59 @@ SPIDriver SPID2; /*==========================================================================*/ /* Driver local functions. */ /*==========================================================================*/ -/* -// Configure the speed of the SPI interface. -static void spi_set_speed(uint8_t ds) { - // We must make a test to see if we are in master mode. - // ds = double speed; +/* Configure the speed of the SPI interface. */ +/* +Static void spi_set_speed(uint8_t ds) { + We must make a test to see if we are in master mode. + + ds = double speed; if (ds == SPI_SPEED_DOUBLE) { - SPIC.CTRL |= (1 << SPI_CLK2X_bp); // double speed. + SPIC.CTRL |= (1 << SPI_CLK2X_bp); double speed. } else { - SPIC.CTRL &= ~(1 << SPI_CLK2X_bp); // simple speed. + SPIC.CTRL &= ~(1 << SPI_CLK2X_bp); simple speed. } } */ - -// Enable the SPI module. -//static void spi_lld_enable(SPIDriver *spip) { -// spip->spi->CTRL |= (1 << SPI_ENABLE_bp); -//} - - +/* Enable the SPI module. */ /* -// Disable the SPI interface. -static void spi_disable(void) { +Static void spi_lld_enable(SPIDriver *spip) { + spip->spi->CTRL |= (1 << SPI_ENABLE_bp); +} +*/ + +/* Disable the SPI interface. */ +/* +Static void spi_disable(void) { SPIC.CTRL &= ~(1 << SPI_ENABLE_bp); } */ +/* Configure the SPI bit order, LSB/MSB first. */ /* -// Configure the SPI bit order, LSB/MSB first. -static void spi_set_bit_order(uint8_t bo) { +Static void spi_set_bit_order(uint8_t bo) { // bo = bit order if (bo == SPI_MSB_FIRST) SPIC.CTRL &= ~(1 << SPI_DORD_bp); else SPIC.CTRL |= (1 << SPI_DORD_bp); } +*/ -// Configure the SPI interface to Master or slave. -static void spi_set_mode(uint8_t mode) { +/* Configure the SPI interface to Master or slave. */ +/* +Static void spi_set_mode(uint8_t mode) { if (mode == SPI_MODE_SLAVE) SPIC.CTRL &= ~(1 << SPI_MASTER_bp); else SPIC.CTRL |= (1 << SPI_MASTER_bp); } +*/ -static void spi_set_stransfer_mode(SPI_MODE_t mode) { +/* +Static void spi_set_stransfer_mode(SPI_MODE_t mode) { switch(mode) { case SPI_TRANSFER_MODE0: SPIC.CTRL = (SPIC.CTRL & ~SPI_MODE_gm) | SPI_MODE_0_gc; @@ -126,14 +131,16 @@ static void spi_set_stransfer_mode(SPI_MODE_t mode) { SPIC.CTRL = (SPIC.CTRL & ~SPI_MODE_gm) | SPI_MODE_0_gc; break; } -}*/ +} +*/ /** * @brief Configure the SPI colck from the System clock. * * @param[in] prescaler the prescaler used to divide the system clock - *//* -static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) { + */ +/* +Static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) { switch(prescaler) { case SPI_PRESCALER_4: SPIC.CTRL = (SPIC.CTRL & ~SPI_PRESCALER_gm) | SPI_PRESCALER_DIV4_gc; @@ -162,7 +169,8 @@ static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) { * * @param[in] il the interrupt level */ -/*static void spi_set_irq_level(SPI_INTLVL_t il) { +/* +Static void spi_set_irq_level(SPI_INTLVL_t il) { switch(il) { case SPI_INT_DISABLE: SPIC.INTCTRL = (SPIC.INTCTRL & ~SPI_INTLVL_gm) | SPI_INTLVL_OFF_gc; @@ -186,25 +194,27 @@ static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) { } } - -void spi_send_byte(uint8_t data) { +Void spi_send_byte(uint8_t data) { SPIC.DATA = data; while(!(SPIC.STATUS & SPI_IF_bm)); } */ -/* - spi_set_speed(SPI_SPEED_SIMPLE); // Configure the speed double. - spi_set_bit_order(SPI_MSB_FIRST); // Configure the bit order. - spi_set_mode(SPI_MODE_MASTER); // Configure the mode to master. - spi_set_stransfer_mode(SPI_TRANSFER_MODE0); // Configure the transfer mode. - spi_set_clock_prescaler(SPI_PRESCALER_4); // Configure the clock prescaler. - spi_set_irq_level(SPI_INT_LEVEL_LOW); // Configure the irq level. - spi_enable(); // Enable the SPI interface. - //spi_select(); // For the chip select. // TODO - spi_send_byte(0xAA); // For the chip select. - //spi_deselect(); // for the chip select. // TODO - */ +/* + * + * Spi_set_speed(SPI_SPEED_SIMPLE); Configure the speed double. + * Spi_set_bit_order(SPI_MSB_FIRST); Configure the bit order. + * Spi_set_mode(SPI_MODE_MASTER); Configure the mode to master. + * Spi_set_stransfer_mode(SPI_TRANSFER_MODE0); Configure the transfer mode. + * Spi_set_clock_prescaler(SPI_PRESCALER_4); Configure the clock prescaler. + * Spi_set_irq_level(SPI_INT_LEVEL_LOW); Configure the irq level. + * Spi_enable(); Enable the SPI interface. + * + * Spi_select(); For the chip select. + * Spi_send_byte(0xAA); For the chip select. + * Spi_deselect(); For the chip select. + */ + /*==========================================================================*/ /* Driver interrupt handlers. */ /*==========================================================================*/ @@ -273,11 +283,11 @@ void spi_lld_start(SPIDriver *spip) { uint8_t dummy; if (&SPID1 == spip) { - // Configures the peripheral. - // Note that some bits are forced: - // SPI interrupt disabled, - // SPI enabled, - // SPI master enabled. + /* Configures the peripheral, */ + /* Note that some bits are forced, */ + /* SPI interrupt disabled, */ + /* SPI enabled, */ + /* SPI master enabled, */ spip->spi->INTCTRL = SPI_INTLVL_OFF_gc; @@ -288,12 +298,12 @@ void spi_lld_start(SPIDriver *spip) { (spip->config->mode) | (spip->config->prescaler); - // Dummy reads before enabling interrupt. + /* Dummy reads before enabling interrupt. */ dummy = spip->spi->STATUS; dummy = spip->spi->DATA; - (void) dummy; // Suppress warning about unused variable. + (void) dummy; /* Suppress warning about unused variable. */ - // Enable SPI interrupts. + /* Enable SPI interrupts. */ spip->spi->INTCTRL = spip->config->irqlevel; } } @@ -307,7 +317,7 @@ void spi_lld_start(SPIDriver *spip) { */ void spi_lld_stop(SPIDriver *spip) { if (spip->state == SPI_READY) { - // Disable the peripheral. + /* Disable the peripheral. */ spip->spi->CTRL &= ~(1 << SPI_ENABLE_bp); } } @@ -324,7 +334,7 @@ void spi_lld_select(SPIDriver *spip) { /** * NOTE: This should only be called in master mode. */ - //spip->config->ssport->out &= ~(1 << spip->config->sspad); + /* Spip->config->ssport->out &= ~(1 << spip->config->sspad); */ } @@ -341,11 +351,12 @@ void spi_lld_unselect(SPIDriver *spip) { /** * NOTE: This should only be called in master mode. */ - //spip->config->ssport->out |= (1 << spip->config->sspad); + /* + * Spip->config->ssport->out |= (1 << spip->config->sspad); + */ } - /** * @brief Exchanges data on the SPI bus. * @details This asynchronous function starts a simultaneous transmit/receive @@ -403,16 +414,16 @@ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) { uint8_t dummy; (void)spip; - // Disable interrupt. + /* Disable interrupt. */ spip->spi->INTCTRL = SPI_INTLVL_OFF_gc; spip->spi->DATA = frame; - while (!(spip->spi->STATUS & SPI_IF_bm)) ; + while (!(spip->spi->STATUS & SPI_IF_bm)); spdr = spip->spi->DATA; dummy = spip->spi->STATUS; dummy = spip->spi->DATA; - (void) dummy; // Suppress warning about unused variable. + (void) dummy; /* Suppress warning about unused variable. */ spip->spi->INTCTRL = SPI_INTLVL_LO_gc; return spdr; diff --git a/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.h b/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.h index 75c151da6..dc08683f9 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.h +++ b/os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.h @@ -35,7 +35,8 @@ * @name SPI Configuration Register * @{ */ -/*#define SPI_CR_SPIE (1 << SPIE) +/* +#define SPI_CR_SPIE (1 << SPIE) #define SPI_CR_SPE (1 << SPE) @@ -55,7 +56,6 @@ #define SPI_CR_SCK_FOSC_128 (3 << SPR0) */ - #define SPI_SPEED_SIMPLE 0 #define SPI_SPEED_DOUBLE 1 @@ -141,7 +141,6 @@ size_t exbytes; \ size_t exidx; - /** * @brief Low level fields of the SPI configuration structure. */ @@ -223,11 +222,15 @@ extern "C" { void spi_lld_abort(SPIDriver *spip); #endif -//#if AVR_SPI_USE_16BIT_POLLED_EXCHANGE -// uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -//#else +/* + #if AVR_SPI_USE_16BIT_POLLED_EXCHANGE + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); + #else +*/ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame); -//#endif +/* + #endif +*/ #ifdef __cplusplus } diff --git a/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.c index 6020c7a7b..2bf5021d6 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.c @@ -86,8 +86,8 @@ void st_lld_init(void) { #if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) TCC0.PER = (F_CPU/OSAL_ST_FREQUENCY) - 1; - TCC0.CTRLA = ( TCC0.CTRLA & ~TC0_CLKSEL_gm ) | TC_CLKSEL_DIV1_gc; - TCC0.INTCTRLA = ( TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm ) | TC_OVFINTLVL_MED_gc; + TCC0.CTRLA = (TCC0.CTRLA & ~TC0_CLKSEL_gm) | TC_CLKSEL_DIV1_gc; + TCC0.INTCTRLA = (TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm) | TC_OVFINTLVL_MED_gc; PMIC.CTRL |= PMIC_MEDLVLEN_bm; sei(); diff --git a/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.h index 0e1185cf6..82ee98e42 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/AVR/XMEGA/LLD/SYSTICKv1/hal_st_lld.h @@ -97,7 +97,7 @@ static inline systime_t st_lld_get_counter(void) { */ static inline void st_lld_start_alarm(systime_t time) { - TCC0.INTCTRLA = ( TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm ) | TC_OVFINTLVL_MED_gc; + TCC0.INTCTRLA = (TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm) | TC_OVFINTLVL_MED_gc; PMIC.CTRL |= PMIC_MEDLVLEN_bm; } diff --git a/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_serial_lld.c index 86236d04f..76531f333 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_serial_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_serial_lld.c @@ -233,8 +233,8 @@ static void usart_cfg_baudrate(SerialDriver *sdp, const SerialConfig *config) { /* BSCALE = 0. */ #define BSCALE 0 uint16_t br = get_bsel(config->speed); - sdp->usart->BAUDCTRLA =(uint8_t)br; - sdp->usart->BAUDCTRLB =(BSCALE << USART_BSCALE0_bp) | (br >> 8); + sdp->usart->BAUDCTRLA = (uint8_t)br; + sdp->usart->BAUDCTRLB = (BSCALE << USART_BSCALE0_bp) | (br >> 8); } /** @@ -263,7 +263,7 @@ static void usart_start(SerialDriver *sdp, const SerialConfig *config) { /* Resetting eventual pending status flags. */ /* Starting the receiver idle loop. */ - /*uart_enter_rx_idle_loop(uartp);*/ + /* Uart_enter_rx_idle_loop(uartp); */ usart_cfg_mpcm(sdp, config); usart_cfg_clk2x(sdp, config); diff --git a/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_uart_lld.c index 06bf504dd..8df9dc99b 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_uart_lld.c @@ -219,8 +219,8 @@ static void usart_cfg_baudrate(UARTDriver *uartp) { /* BSCALE = 0. */ #define BSCALE 0 uint16_t br = get_bsel(uartp->config->speed); - uartp->usart->BAUDCTRLA =(uint8_t)br; - uartp->usart->BAUDCTRLB =(BSCALE << USART_BSCALE0_bp) | (br >> 8); + uartp->usart->BAUDCTRLA = (uint8_t)br; + uartp->usart->BAUDCTRLB = (BSCALE << USART_BSCALE0_bp) | (br >> 8); } /** @@ -232,10 +232,8 @@ static void usart_cfg_baudrate(UARTDriver *uartp) { static void usart_stop(UARTDriver *uartp) { /* Stops RX and TX DMA channels. */ - /* - dmaStreamDisable(uartp->dmarx); - dmaStreamDisable(uartp->dmatx); - */ + /* DmaStreamDisable(uartp->dmarx); */ + /* DmaStreamDisable(uartp->dmatx); */ /* Stops USART operations. */ uartp->usart->CTRLB &= ~(USART_RXEN_bm); /* Disable the USART receiver. */ @@ -256,7 +254,7 @@ static void usart_start(UARTDriver *uartp) { /* Resetting eventual pending status flags. */ /* Starting the receiver idle loop. */ - /*uart_enter_rx_idle_loop(uartp);*/ + /* Uart_enter_rx_idle_loop(uartp); */ usart_cfg_mpcm(uartp); /* Set the multi processor communication mode. */ usart_cfg_clk2x(uartp); /* Set the USART speed (Normal/Double). */ @@ -266,8 +264,8 @@ static void usart_start(UARTDriver *uartp) { usart_cfg_pmode(uartp); /* Set the parity mode. */ usart_cfg_chsize(uartp);/* Set the character size. */ usart_cfg_baudrate(uartp); /* Set the baud rate. */ - uartp->usart->CTRLB |= (USART_RXEN_bm); /* enable the USART receiver. */ - uartp->usart->CTRLB |= (USART_TXEN_bm); /* enable the USART transmitter. */ + uartp->usart->CTRLB |= (USART_RXEN_bm); /* Enable the USART receiver. */ + uartp->usart->CTRLB |= (USART_TXEN_bm); /* Enable the USART transmitter. */ } /*==========================================================================*/ @@ -284,7 +282,7 @@ OSAL_IRQ_HANDLER(USARTC0_TXC_vect) { OSAL_IRQ_PROLOGUE(); - /*serve_usart_irq(&UARTD1);*/ + /* @TODO serve_usart_irq(&UARTD1);*/ OSAL_IRQ_EPILOGUE(); } @@ -298,7 +296,7 @@ OSAL_IRQ_HANDLER(USARTC0_RXC_vect) { OSAL_IRQ_PROLOGUE(); - /*serve_usart_irq(&UARTD1);*/ + /* @TODO serve_usart_irq(&UARTD1);*/ OSAL_IRQ_EPILOGUE(); } @@ -312,7 +310,7 @@ OSAL_IRQ_HANDLER(USARTC0_DRE_vect) { OSAL_IRQ_PROLOGUE(); - /*serve_usart_irq(&UARTD1);*/ + /* @TODO serve_usart_irq(&UARTD1);*/ OSAL_IRQ_EPILOGUE(); } @@ -333,8 +331,8 @@ void uart_lld_init(void) { /* Driver initialization. */ uartObjectInit(&USART1D); USART1D.usart = &USARTC0; - /*USART1D.usart->CTRLC = 0;*/ - /*USART1D.usart->BAUDCTRLA = 0;*/ + /* USART1D.usart->CTRLC = 0; */ + /* USART1D.usart->BAUDCTRLA = 0; */ #endif #if AVR_UART_USE_USART2 == TRUE @@ -457,7 +455,6 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { (void)uartp; (void)n; (void)rxbuf; - } /** diff --git a/os/hal/ports/AVR/XMEGA/LLD/WDGv1/hal_wdg_lld.c b/os/hal/ports/AVR/XMEGA/LLD/WDGv1/hal_wdg_lld.c index e4d406dc1..1a2502644 100644 --- a/os/hal/ports/AVR/XMEGA/LLD/WDGv1/hal_wdg_lld.c +++ b/os/hal/ports/AVR/XMEGA/LLD/WDGv1/hal_wdg_lld.c @@ -72,7 +72,7 @@ static void wdg_enable(WDGDriver *wdgp) { uint8_t cfg = wdgp->wdg->CTRL | WDT_ENABLE_bm | WDT_CEN_bm; CCP = CCP_IOREG_gc; wdgp->wdg->CTRL = cfg; - + while (wdg_get_sync_busy_flag(wdgp)); } @@ -102,23 +102,6 @@ static void wdg_disable(WDGDriver *wdgp) { wdgp->wdg->CTRL = cfg; } -/** - * @brief Return status of window mode enable bit. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * @return The status of the watchdog module - * @retval true The WD Window Mode is enabled. - * @retval false The WD Eindow Mode is not enabled. - */ -/*static bool wdg_is_window_mode_enabled(WDGDriver *wdgp) { - - if (wdgp->wdg->WINCTRL & WDT_WEN_bm) - return true; - else - return false; -} -*/ - /** * @brief Enable watchdog window mode. *