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STM32/RCCv1: fix thresholds for PLLP and PLLR values 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14634 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
akscram 2021-08-10 22:33:42 +00:00
parent c528813aae
commit 6ad1a238cd
1 changed files with 4 additions and 2 deletions
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6
os/hal/ports/STM32/LLD/RCCv1/stm32_pll_v2.inc
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@ -211,7 +211,8 @@
/**
* @brief STM32_PLLP field.
*/
#if ((STM32_PLLP_VALUE_MIN >= STM32_PLLP_VALUE_MIN) && (STM32_PLLP_VALUE_MAX <= 32)) || \
#if ((STM32_PLLP_VALUE >= STM32_PLLP_VALUE_MIN) && \
(STM32_PLLP_VALUE <= STM32_PLLP_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLLP ((STM32_PLLP_VALUE - 1) << 17)
#else
@ -282,7 +283,8 @@
/**
* @brief STM32_PLLR field.
*/
#if ((STM32_PLLR_VALUE >= STM32_PLLR_VALUE_MIN) && (STM32_PLLR_VALUE <= STM32_PLLP_VALUE_MAX)) || \
#if ((STM32_PLLR_VALUE >= STM32_PLLR_VALUE_MIN) && \
(STM32_PLLR_VALUE <= STM32_PLLR_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLLR ((STM32_PLLR_VALUE - 1) << 29)
#else