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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7190 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2014-08-25 08:45:58 +00:00
parent 2d9efb0eaf
commit 6ccef4b00a
3 changed files with 29 additions and 13 deletions
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11
os/hal/ports/STM32/STM32F0xx/adc_lld.c
View File

@ -245,13 +245,15 @@ void adc_lld_stop(ADCDriver *adcp) {
* @notapi * @notapi
*/ */
void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode; uint32_t mode, cfgr1;
const ADCConversionGroup *grpp = adcp->grpp; const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/ /* DMA setup.*/
mode = adcp->dmamode; mode = adcp->dmamode;
cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN;
if (grpp->circular) { if (grpp->circular) {
mode |= STM32_DMA_CR_CIRC; mode |= STM32_DMA_CR_CIRC;
cfgr1 |= ADC_CFGR1_DMACFG;
if (adcp->depth > 1) { if (adcp->depth > 1) {
/* If circular buffer depth > 1, then the half transfer interrupt /* If circular buffer depth > 1, then the half transfer interrupt
is enabled in order to allow streaming processing.*/ is enabled in order to allow streaming processing.*/
@ -273,8 +275,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adc->CHSELR = grpp->chselr; adcp->adc->CHSELR = grpp->chselr;
/* ADC configuration and start.*/ /* ADC configuration and start.*/
adcp->adc->CFGR1 = grpp->cfgr1 | ADC_CFGR1_CONT | ADC_CFGR1_DMACFG | adcp->adc->CFGR1 = cfgr1;
ADC_CFGR1_DMAEN;
adcp->adc->CR |= ADC_CR_ADSTART; adcp->adc->CR |= ADC_CR_ADSTART;
} }

27
os/hal/ports/STM32/STM32F0xx/adc_lld.h
View File

@ -46,20 +46,30 @@
/** @} */ /** @} */
/** /**
* @name Resolution * @name CFGR1 register configuration helpers
* @{ * @{
*/ */
#define ADC_CFGR1_RES_12BIT (0 << 3) #define ADC_CFGR1_RES_12BIT (0 << 3)
#define ADC_CFGR1_RES_10BIT (1 << 3) #define ADC_CFGR1_RES_10BIT (1 << 3)
#define ADC_CFGR1_RES_8BIT (2 << 3) #define ADC_CFGR1_RES_8BIT (2 << 3)
#define ADC_CFGR1_RES_6BIT (3 << 3) #define ADC_CFGR1_RES_6BIT (3 << 3)
#define ADC_CFGR1_EXTSEL_MASK (15 << 6)
#define ADC_CFGR1_EXTSEL_SRC(n) ((n) << 6)
#define ADC_CFGR1_EXTEN_MASK (3 << 10)
#define ADC_CFGR1_EXTEN_DISABLED (0 << 10)
#define ADC_CFGR1_EXTEN_RISING (1 << 10)
#define ADC_CFGR1_EXTEN_FALLING (2 << 10)
#define ADC_CFGR1_EXTEN_BOTH (3 << 10)
/** @} */ /** @} */
/** /**
* @name Threashold register initializer * @name Threashold register initializer
* @{ * @{
*/ */
#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low)) #define ADC_TR(low, high) (((uint32_t)(high) << 16) | \
(uint32_t)(low))
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/
@ -210,6 +220,11 @@ typedef struct {
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
/** /**
* @brief ADC CFGR1 register initialization data. * @brief ADC CFGR1 register initialization data.
* @note The bits DMAEN and DMACFG are enforced internally
* to the driver, keep them to zero.
* @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be
* specified in continuous more or if the buffer depth is
* greater than one.
*/ */
uint32_t cfgr1; uint32_t cfgr1;
/** /**

4
testhal/STM32/STM32F0xx/ADC/main.c
View File

@ -57,7 +57,7 @@ static const ADCConversionGroup adcgrpcfg1 = {
ADC_GRP1_NUM_CHANNELS, ADC_GRP1_NUM_CHANNELS,
NULL, NULL,
adcerrorcallback, adcerrorcallback,
ADC_CFGR1_RES_12BIT, /* CFGRR1 */ ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGRR1 */
ADC_TR(0, 0), /* TR */ ADC_TR(0, 0), /* TR */
ADC_SMPR_SMP_1P5, /* SMPR */ ADC_SMPR_SMP_1P5, /* SMPR */
ADC_CHSELR_CHSEL10 /* CHSELR */ ADC_CHSELR_CHSEL10 /* CHSELR */
@ -73,7 +73,7 @@ static const ADCConversionGroup adcgrpcfg2 = {
ADC_GRP2_NUM_CHANNELS, ADC_GRP2_NUM_CHANNELS,
adccallback, adccallback,
adcerrorcallback, adcerrorcallback,
ADC_CFGR1_RES_12BIT, /* CFGRR1 */ ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGRR1 */
ADC_TR(0, 0), /* TR */ ADC_TR(0, 0), /* TR */
ADC_SMPR_SMP_28P5, /* SMPR */ ADC_SMPR_SMP_28P5, /* SMPR */
ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 |