Fixed bug #1050.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13085 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
a6b5e77f22
commit
6cdb5ed5fe
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@ -51,6 +51,22 @@
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
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STM32_DAC2_CH2_DMA_CHN)
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#define DAC3_CH1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC3_CH1_DMA_STREAM, \
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STM32_DAC3_CH1_DMA_CHN)
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#define DAC3_CH2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC3_CH2_DMA_STREAM, \
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STM32_DAC3_CH2_DMA_CHN)
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#define DAC4_CH1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC4_CH1_DMA_STREAM, \
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STM32_DAC4_CH1_DMA_CHN)
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#define DAC4_CH2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_DAC_DAC4_CH2_DMA_STREAM, \
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STM32_DAC4_CH2_DMA_CHN)
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#define CHANNEL_DATA_OFFSET 3U
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/*===========================================================================*/
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@ -77,12 +93,32 @@ DACDriver DACD3;
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DACDriver DACD4;
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#endif
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/** @brief DAC3 CH1 driver identifier.*/
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#if STM32_DAC_USE_DAC3_CH1 || defined(__DOXYGEN__)
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DACDriver DACD5;
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#endif
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/** @brief DAC3 CH2 driver identifier.*/
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#if (STM32_DAC_USE_DAC3_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
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DACDriver DACD6;
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#endif
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/** @brief DAC4 CH1 driver identifier.*/
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#if STM32_DAC_USE_DAC4_CH1 || defined(__DOXYGEN__)
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DACDriver DACD7;
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#endif
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/** @brief DAC4 CH2 driver identifier.*/
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#if (STM32_DAC_USE_DAC4_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
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DACDriver DACD8;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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#if STM32_DAC_USE_DAC1_CH1 == TRUE
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static const dacparams_t dma1_ch1_params = {
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static const dacparams_t dac1_ch1_params = {
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.dac = DAC1,
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.dataoffset = 0U,
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.regshift = 0U,
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@ -101,7 +137,7 @@ static const dacparams_t dma1_ch1_params = {
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#endif
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#if STM32_DAC_USE_DAC1_CH2 == TRUE
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static const dacparams_t dma1_ch2_params = {
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static const dacparams_t dac1_ch2_params = {
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.dac = DAC1,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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@ -120,7 +156,7 @@ static const dacparams_t dma1_ch2_params = {
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#endif
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#if STM32_DAC_USE_DAC2_CH1 == TRUE
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static const dacparams_t dma2_ch1_params = {
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static const dacparams_t dac2_ch1_params = {
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.dac = DAC2,
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.dataoffset = 0U,
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.regshift = 0U,
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@ -139,7 +175,7 @@ static const dacparams_t dma2_ch1_params = {
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#endif
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#if STM32_DAC_USE_DAC2_CH2 == TRUE
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static const dacparams_t dma1_ch2_params = {
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static const dacparams_t dac2_ch2_params = {
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.dac = DAC2,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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@ -157,6 +193,82 @@ static const dacparams_t dma1_ch2_params = {
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};
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#endif
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#if STM32_DAC_USE_DAC3_CH1 == TRUE
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static const dacparams_t dac3_ch1_params = {
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.dac = DAC3,
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.dataoffset = 0U,
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.regshift = 0U,
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.regmask = 0xFFFF0000U,
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.dmastream = STM32_DAC_DAC3_CH1_DMA_STREAM,
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#if STM32_DMA_SUPPORTS_DMAMUX
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.peripheral = STM32_DMAMUX1_DAC3_CH1,
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#endif
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.dmamode = STM32_DMA_CR_CHSEL(DAC3_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC3_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC3_CH1_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC3_CH2 == TRUE
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static const dacparams_t dac3_ch2_params = {
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.dac = DAC3,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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.regmask = 0x0000FFFFU,
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.dmastream = STM32_DAC_DAC3_CH2_DMA_STREAM,
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#if STM32_DMA_SUPPORTS_DMAMUX
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.peripheral = STM32_DMAMUX1_DAC3_CH2,
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#endif
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.dmamode = STM32_DMA_CR_CHSEL(DAC3_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC3_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC3_CH2_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC4_CH1 == TRUE
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static const dacparams_t dac4_ch1_params = {
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.dac = DAC4,
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.dataoffset = 0U,
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.regshift = 0U,
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.regmask = 0xFFFF0000U,
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.dmastream = STM32_DAC_DAC4_CH1_DMA_STREAM,
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#if STM32_DMA_SUPPORTS_DMAMUX
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.peripheral = STM32_DMAMUX1_DAC4_CH1,
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#endif
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.dmamode = STM32_DMA_CR_CHSEL(DAC4_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC4_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC4_CH1_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC4_CH2 == TRUE
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static const dacparams_t dac4_ch2_params = {
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.dac = DAC4,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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.regmask = 0x0000FFFFU,
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.dmastream = STM32_DAC_DAC4_CH2_DMA_STREAM,
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#if STM32_DMA_SUPPORTS_DMAMUX
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.peripheral = STM32_DMAMUX1_DAC4_CH2,
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#endif
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.dmamode = STM32_DMA_CR_CHSEL(DAC4_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC4_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC4_CH2_IRQ_PRIORITY
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};
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#endif
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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@ -202,27 +314,51 @@ void dac_lld_init(void) {
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#if STM32_DAC_USE_DAC1_CH1
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dacObjectInit(&DACD1);
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DACD1.params = &dma1_ch1_params;
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DACD1.params = &dac1_ch1_params;
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DACD1.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC1_CH2
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dacObjectInit(&DACD2);
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DACD2.params = &dma1_ch2_params;
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DACD2.params = &dac1_ch2_params;
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DACD2.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC2_CH1
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dacObjectInit(&DACD3);
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DACD3.params = &dma2_ch1_params;
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DACD3.params = &dac2_ch1_params;
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DACD3.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC2_CH2
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dacObjectInit(&DACD4);
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DACD4.params = &dma2_ch2_params;
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DACD4.params = &dac2_ch2_params;
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DACD4.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC3_CH1
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dacObjectInit(&DACD5);
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DACD5.params = &dac3_ch1_params;
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DACD5.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC3_CH2
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dacObjectInit(&DACD6);
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DACD6.params = &dac3_ch2_params;
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DACD6.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC4_CH1
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dacObjectInit(&DACD7);
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DACD7.params = &dac4_ch1_params;
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DACD7.dma = NULL;
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#endif
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#if STM32_DAC_USE_DAC4_CH2
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dacObjectInit(&DACD8);
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DACD8.params = &dac4_ch2_params;
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DACD8.dma = NULL;
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#endif
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}
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/**
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@ -265,6 +401,33 @@ void dac_lld_start(DACDriver *dacp) {
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channel = 1;
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}
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#endif
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#if STM32_DAC_USE_DAC3_CH1
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if (&DACD5 == dacp) {
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rccEnableDAC3(true);
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}
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#endif
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#if STM32_DAC_USE_DAC3_CH2
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if (&DACD6 == dacp) {
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rccEnableDAC3(true);
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channel = 1;
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}
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#endif
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#if STM32_DAC_USE_DAC4_CH1
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if (&DACD7 == dacp) {
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rccEnableDAC4(true);
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}
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#endif
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#if STM32_DAC_USE_DAC4_CH2
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if (&DACD8 == dacp) {
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rccEnableDAC4(true);
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channel = 1;
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}
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#endif
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/* Enabling DAC in SW triggering mode initially, initializing data to
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zero.*/
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#if STM32_DAC_DUAL_MODE == FALSE
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@ -303,7 +466,7 @@ void dac_lld_stop(DACDriver *dacp) {
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#if STM32_DAC_USE_DAC1_CH1
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if (&DACD1 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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rccDisableDAC1();
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}
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}
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@ -311,7 +474,7 @@ void dac_lld_stop(DACDriver *dacp) {
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#if STM32_DAC_USE_DAC1_CH2
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if (&DACD2 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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rccDisableDAC1();
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}
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}
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@ -319,7 +482,7 @@ void dac_lld_stop(DACDriver *dacp) {
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#if STM32_DAC_USE_DAC2_CH1
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if (&DACD3 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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rccDisableDAC2();
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}
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}
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@ -327,11 +490,43 @@ void dac_lld_stop(DACDriver *dacp) {
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#if STM32_DAC_USE_DAC2_CH2
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if (&DACD4 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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rccDisableDAC2();
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}
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}
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#endif
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#if STM32_DAC_USE_DAC3_CH1
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if (&DACD5 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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rccDisableDAC3();
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}
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}
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#endif
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#if STM32_DAC_USE_DAC3_CH2
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if (&DACD6 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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rccDisableDAC3();
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}
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}
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#endif
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#if STM32_DAC_USE_DAC4_CH1
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if (&DACD7 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
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rccDisableDAC4();
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}
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}
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#endif
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#if STM32_DAC_USE_DAC4_CH2
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if (&DACD8 == dacp) {
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if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
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rccDisableDAC4();
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}
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}
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#endif
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}
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}
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@ -360,7 +555,8 @@ void dac_lld_put_channel(DACDriver *dacp,
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*(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = (uint32_t)sample;
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#endif
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}
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#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2)
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#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
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STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
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else {
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dacp->params->dac->DHR12R2 = (uint32_t)sample;
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}
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@ -377,7 +573,8 @@ void dac_lld_put_channel(DACDriver *dacp,
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*(&dacp->params->dac->DHR12L1 + dacp->params->dataoffset) = (uint32_t)sample;
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#endif
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}
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#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2)
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#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
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STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
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else {
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dacp->params->dac->DHR12L2 = (uint32_t)sample;
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}
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@ -394,7 +591,8 @@ void dac_lld_put_channel(DACDriver *dacp,
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*(&dacp->params->dac->DHR8R1 + dacp->params->dataoffset) = (uint32_t)sample;
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#endif
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}
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#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2)
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#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
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STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
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else {
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dacp->params->dac->DHR8R2 = (uint32_t)sample;
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}
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@ -91,6 +91,42 @@
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#define STM32_DAC_USE_DAC2_CH2 FALSE
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#endif
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/**
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* @brief DAC3 CH1 driver enable switch.
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* @details If set to @p TRUE the support for DAC3 channel 1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_DAC_USE_DAC3_CH1) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_DAC3_CH1 FALSE
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#endif
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/**
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* @brief DAC3 CH2 driver enable switch.
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* @details If set to @p TRUE the support for DAC3 channel 2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_DAC_USE_DAC3_CH2) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_DAC3_CH2 FALSE
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#endif
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/**
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* @brief DAC4 CH1 driver enable switch.
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* @details If set to @p TRUE the support for DAC4 channel 1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_DAC_USE_DAC4_CH1) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_DAC4_CH1 FALSE
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#endif
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/**
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* @brief DAC4 CH2 driver enable switch.
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* @details If set to @p TRUE the support for DAC4 channel 2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_DAC_USE_DAC4_CH2) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_DAC4_CH2 FALSE
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#endif
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/**
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* @brief DAC1 CH1 interrupt priority level setting.
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*/
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@ -119,6 +155,34 @@
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#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC3 CH1 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC_DAC3_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
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#endif
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||||
|
||||
/**
|
||||
* @brief DAC3 CH2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC3_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC4 CH1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC4_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC4 CH2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC4_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
|
|
@ -146,12 +210,66 @@
|
|||
#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC3 CH1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC3_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC3 CH2 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC3_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC4 CH1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC4_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DAC4 CH2 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_DAC_DAC4_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* Handling missing registry keys.*/
|
||||
#if !defined(STM32_HAS_DAC1_CH1)
|
||||
#define STM32_HAS_DAC1_CH1 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC1_CH2)
|
||||
#define STM32_HAS_DAC1_CH2 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC2_CH1)
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC2_CH2)
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC3_CH1)
|
||||
#define STM32_HAS_DAC3_CH1 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC3_CH2)
|
||||
#define STM32_HAS_DAC3_CH2 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC4_CH1)
|
||||
#define STM32_HAS_DAC4_CH1 FALSE
|
||||
#endif
|
||||
#if !defined(STM32_HAS_DAC4_CH2)
|
||||
#define STM32_HAS_DAC4_CH2 FALSE
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1
|
||||
#error "DAC1 CH1 not present in the selected device"
|
||||
#endif
|
||||
|
|
@ -168,12 +286,31 @@
|
|||
#error "DAC2 CH2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2) && STM32_DAC_DUAL_MODE
|
||||
#if STM32_DAC_USE_DAC3_CH1 && !STM32_HAS_DAC3_CH1
|
||||
#error "DAC3 CH1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH2 && !STM32_HAS_DAC3_CH2
|
||||
#error "DAC3 CH2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH1 && !STM32_HAS_DAC4_CH1
|
||||
#error "DAC4 CH1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH2 && !STM32_HAS_DAC4_CH2
|
||||
#error "DAC4 CH2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2 || \
|
||||
STM32_DAC_USE_DAC3_CH2 || STM32_DAC_USE_DAC4_CH2) && STM32_DAC_DUAL_MODE
|
||||
#error "DACx CH2 cannot be used independently in dual mode"
|
||||
#endif
|
||||
|
||||
#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \
|
||||
!STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2
|
||||
!STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2 && \
|
||||
!STM32_DAC_USE_DAC3_CH1 && !STM32_DAC_USE_DAC3_CH2 && \
|
||||
!STM32_DAC_USE_DAC4_CH1 && !STM32_DAC_USE_DAC4_CH2
|
||||
#error "DAC driver activated but no DAC peripheral assigned"
|
||||
#endif
|
||||
|
||||
|
|
@ -197,6 +334,26 @@
|
|||
#error "Invalid IRQ priority assigned to DAC2 CH2"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH1_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to DAC3 CH1"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH2_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to DAC3 CH2"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH1_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to DAC4 CH1"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH2_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to DAC4 CH2"
|
||||
#endif
|
||||
|
||||
/* The following checks are only required when there is a DMA able to
|
||||
reassign streams to different channels.*/
|
||||
#if STM32_ADVANCED_DMA
|
||||
|
|
@ -218,6 +375,22 @@
|
|||
#error "DAC2 CH2 DMA stream not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH1 && !defined(STM32_DAC_DAC3_CH1_DMA_STREAM)
|
||||
#error "DAC3 CH1 DMA stream not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH2 && !defined(STM32_DAC_DAC3_CH2_DMA_STREAM)
|
||||
#error "DAC3 CH2 DMA stream not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH1 && !defined(STM32_DAC_DAC4_CH1_DMA_STREAM)
|
||||
#error "DAC4 CH1 DMA stream not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH2 && !defined(STM32_DAC_DAC4_CH2_DMA_STREAM)
|
||||
#error "DAC4 CH2 DMA stream not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_DMA_SUPPORTS_DMAMUX
|
||||
|
||||
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
|
||||
|
|
@ -243,6 +416,26 @@
|
|||
#error "invalid DMA stream associated to DAC2 CH2"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC3_CH1_DMA_STREAM, STM32_DAC3_CH1_DMA_MSK)
|
||||
#error "invalid DMA stream associated to DAC1 CH1"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC3_CH2_DMA_STREAM, STM32_DAC3_CH2_DMA_MSK)
|
||||
#error "invalid DMA stream associated to DAC1 CH2"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH1 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC4_CH1_DMA_STREAM, STM32_DAC4_CH1_DMA_MSK)
|
||||
#error "invalid DMA stream associated to DAC2 CH1"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH2 && \
|
||||
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC4_CH2_DMA_STREAM, STM32_DAC4_CH2_DMA_MSK)
|
||||
#error "invalid DMA stream associated to DAC2 CH2"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
|
||||
|
||||
#endif /* STM32_ADVANCED_DMA */
|
||||
|
|
@ -267,6 +460,26 @@
|
|||
#error "Invalid DMA priority assigned to DAC2 CH2"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to DAC3 CH1"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH2 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH2_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to DAC3 CH2"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to DAC4 CH1"
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH2 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH2_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to DAC4 CH2"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
|
@ -410,6 +623,22 @@ extern DACDriver DACD3;
|
|||
extern DACDriver DACD4;
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH1 && !defined(__DOXYGEN__)
|
||||
extern DACDriver DACD5;
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC3_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
|
||||
extern DACDriver DACD6;
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH1 && !defined(__DOXYGEN__)
|
||||
extern DACDriver DACD7;
|
||||
#endif
|
||||
|
||||
#if STM32_DAC_USE_DAC4_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
|
||||
extern DACDriver DACD8;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@
|
|||
*****************************************************************************
|
||||
|
||||
*** Next ***
|
||||
- HAL: Added support for DAC3 and DAC4 in STM32 DACv1 driver.
|
||||
- NIL: New functions: chSemResetWithMessageI() and chSemResetWithMessage().
|
||||
- RT: New functions: chSemResetWithMessageI() and chSemResetWithMessage().
|
||||
- HAL: Added canTryAbortX() function to CAN driver, implemented
|
||||
|
|
@ -130,6 +131,8 @@
|
|||
- HAL: Added a new interface for range-finder devices (used by EX).
|
||||
- HAL: Added mcuconf.h updater tool for STM32F407 (backported to 19.1.1).
|
||||
- NIL: Integrated NIL 4.0.
|
||||
- FIX: Fixed wrong clock disable check in STM32 DACv1 driver (bug #1050)
|
||||
(backported to 19.1.4)(backported to 18.2.3).
|
||||
- FIX: Fixed clock tree differences in STM32F4 family (bug #1049)
|
||||
(backported to 19.1.4)(backported to 18.2.3).
|
||||
- FIX: Fixed wrong debug check in STM32 I2Cv1 driver (bug #1048)
|
||||
|
|
|
|||
Loading…
Reference in New Issue