diff --git a/os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c
index a42151699..0c5e5b3a6 100644
--- a/os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c
+++ b/os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c
@@ -118,6 +118,9 @@ void wspi_lld_init(void) {
   WSPID2.ospi       = OCTOSPI2;
   WSPID2.mdma       = NULL;
 #endif
+
+  /* Shared unit, enabling it here.*/
+  rccEnableOCTOSPIM(false);
 }
 
 /**
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
index eaad79b58..820373f42 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
@@ -1580,6 +1580,34 @@ __STATIC_INLINE void rccResetAHB4(uint32_t mask) {
 #define rccResetOCTOSPI2() rccResetAHB3(RCC_AHB3RSTR_OSPI2RST)
 /** @} */
 
+/**
+ * @name    OCTOSPIM peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the OCTOSPIM peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOCTOSPIM(lp) rccEnableAHB3(RCC_AHB3ENR_IOMNGREN, lp)
+
+/**
+ * @brief   Disables the OCTOSPIM peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableOCTOSPIM() rccDisableAHB3(RCC_AHB3ENR_IOMNGREN)
+
+/**
+ * @brief   Resets the OCTOSPIM peripheral.
+ *
+ * @api
+ */
+#define rccResetOCTOSPIM() rccResetAHB3(RCC_AHB3RSTR_IOMNGRRST)
+/** @} */
+
 /**
  * @name    RNG peripherals specific RCC operations
  * @{