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Fixed a problem in PAL callbacks STM32 LLDs. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10547 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-09-03 17:10:49 +00:00
parent 8651533a88
commit 6ddf9cf1ee
3 changed files with 22 additions and 19 deletions
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15
os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
View File

@ -206,7 +206,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
iopadid_t pad,
ioeventmode_t mode) {
uint32_t padmask, cridx, crmask, portidx;
uint32_t padmask, cridx, croff, crmask, portidx;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@ -219,14 +219,15 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Index and mask of the SYSCFG CR register to be used.*/
cridx = (uint32_t)pad >> 2U;
crmask = ~(0xFU << (((uint32_t)pad & 3U) * 4U));
croff = ((uint32_t)pad & 3U) * 4U;
crmask = ~(0xFU << croff);
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = (uint32_t)port >> 10U;
portidx = ((uint32_t)port >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | portidx;
AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | (portidx << croff);
/* Programming edge registers.*/
if (mode & PAL_EVENT_MODE_RISING_EDGE)
@ -245,7 +246,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
/**
* @brief Pad event disable.
* @details This function also disables previously programmed event callbacks.
* @details This function disables previously programmed event callbacks.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
@ -271,7 +272,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = (uint32_t)port >> 10U;
portidx = ((uint32_t)port >> 10U) & 0xFU;
crport = (AFIO->EXTICR[cridx] >> croff) & 0xFU;
@ -283,12 +284,12 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
EXTI->RTSR = rtsr1 & ~padmask;
EXTI->FTSR = ftsr1 & ~padmask;
EXTI->PR = padmask;
}
#if PAL_USE_CALLBACKS || PAL_USE_WAIT
/* Callback cleared and/or thread reset.*/
_pal_clear_event(pad);
#endif
}
}
#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */

11
os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
View File

@ -235,7 +235,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
iopadid_t pad,
ioeventmode_t mode) {
uint32_t padmask, cridx, crmask, portidx;
uint32_t padmask, cridx, croff, crmask, portidx;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@ -248,14 +248,15 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Index and mask of the SYSCFG CR register to be used.*/
cridx = (uint32_t)pad >> 2U;
crmask = ~(0xFU << (((uint32_t)pad & 3U) * 4U));
croff = ((uint32_t)pad & 3U) * 4U;
crmask = ~(0xFU << croff);
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = (uint32_t)port >> 10U;
portidx = ((uint32_t)port >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | portidx;
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
/* Programming edge registers.*/
if (mode & PAL_EVENT_MODE_RISING_EDGE)
@ -300,7 +301,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = (uint32_t)port >> 10U;
portidx = ((uint32_t)port >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;

15
os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
View File

@ -231,7 +231,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
iopadid_t pad,
ioeventmode_t mode) {
uint32_t padmask, cridx, crmask, portidx;
uint32_t padmask, cridx, croff, crmask, portidx;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@ -244,14 +244,15 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Index and mask of the SYSCFG CR register to be used.*/
cridx = (uint32_t)pad >> 2U;
crmask = ~(0xFU << (((uint32_t)pad & 3U) * 4U));
croff = ((uint32_t)pad & 3U) * 4U;
crmask = ~(0xFU << croff);
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = (uint32_t)port >> 10U;
portidx = ((uint32_t)port >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | portidx;
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
/* Programming edge registers.*/
if (mode & PAL_EVENT_MODE_RISING_EDGE)
@ -280,8 +281,8 @@ void _pal_lld_enablepadevent(ioportid_t port,
void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
uint32_t padmask, rtsr1, ftsr1;
rtsr1 = EXTI->RTSR1;
ftsr1 = EXTI->FTSR1;
rtsr1 = EXTI->RTSR;
ftsr1 = EXTI->FTSR;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@ -296,7 +297,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = (uint32_t)port >> 10U;
portidx = ((uint32_t)port >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;