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USB-related changes for STM32G0B1 devices. To be tested. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14919 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-10-19 09:52:16 +00:00
parent 8c021bfac5
commit 6de1cfd7f8
11 changed files with 232 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
demos/STM32/RT-STM32G0B1RE-NUCLEO64/cfg/mcuconf.h
View File

@ -58,6 +58,7 @@
#define STM32_PWR_PDCRF (0U)
#define STM32_HSIDIV_VALUE 1
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED FALSE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
@ -77,7 +78,8 @@
/*
* Peripherals clocks and sources.
*/
#define STM32_USBSEL STM32_USBSEL_PLLQCLK
#define STM32_FDCANSEL STM32_FDCANSEL_PCLK
#define STM32_USBSEL STM32_USBSEL_HSI48
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
@ -85,7 +87,9 @@
#define STM32_LPUART2SEL STM32_LPUART2SEL_SYSCLK
#define STM32_CECSEL STM32_CECSEL_HSI16DIV
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK
#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
#define STM32_I2S2SEL STM32_I2S2SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK
#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
@ -293,8 +297,7 @@
*/
#define STM32_USB_USE_USB1 FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
/*
* WDG driver system settings.

17
os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
View File

@ -62,6 +62,7 @@
/*===========================================================================*/
#if STM32_RCC_HAS_HSI48 == TRUE
#if defined(RCC_CRRCR_HSI48ON)
__STATIC_INLINE void hsi48_enable(void) {
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
@ -74,6 +75,22 @@ __STATIC_INLINE void hsi48_disable(void) {
RCC->CRRCR &= ~RCC_CRRCR_HSI48ON;
}
#endif /* defined(RCC_CRRCR_HSI48ON) */
#if defined(RCC_CR_HSI48ON)
__STATIC_INLINE void hsi48_enable(void) {
RCC->CR |= RCC_CR_HSI48ON;
while ((RCC->CR & RCC_CR_HSI48RDY) == 0U) {
/* Waiting for HSI48 activation.*/
}
}
__STATIC_INLINE void hsi48_disable(void) {
RCC->CR &= ~RCC_CR_HSI48ON;
}
#endif /* defined(RCC_CR_HSI48ON) */
#endif /* STM32_RCC_HAS_HSI48 == TRUE */
__STATIC_INLINE void hsi48_init(void) {

7
os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c
View File

@ -36,6 +36,11 @@
#define EPR_EP_TYPE_IS_ISO(bits) ((bits & EPR_EP_TYPE_MASK) == EPR_EP_TYPE_ISO)
/* Addressing differences in headers.*/
#if !defined(USB_CNTR_L2RES) && defined(USB_CNTR_RESUME)
#define USB_CNTR_L2RES USB_CNTR_RESUME
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -759,7 +764,7 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
udp = USB_GET_DESCRIPTOR(ep);
pmap = USB_ADDR2PTR(udp->RXADDR0);
for (n = 0; n < 4; n++) {
*(uint16_t *)buf = (uint16_t)*pmap++;
*(uint16_t *)(void *)buf = (uint16_t)*pmap++;
buf += 2;
}
}

14
os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.h
View File

@ -131,6 +131,10 @@
#error "USB driver activated but no USB peripheral assigned"
#endif
#if !defined(STM32_USBCLK)
#error "STM32_USBCLK not defined"
#endif
#if STM32_USB_USE_USB1 && \
(STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_USB1_HP_IRQ_PRIORITY)
@ -166,6 +170,12 @@
#error "invalid STM32_USB_48MHZ_DELTA setting, it must not exceed 250000"
#endif
/* Allowing for a small tolerance.*/
#if (STM32_USBCLK < (48000000 - STM32_USB_48MHZ_DELTA)) || \
(STM32_USBCLK > (48000000 + STM32_USB_48MHZ_DELTA))
#error "the USB USBv1 driver requires a 48MHz clock"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -473,9 +483,9 @@ struct USBDriver {
*/
#define usb_lld_wakeup_host(usbp) \
do { \
STM32_USB->CNTR |= USB_CNTR_RESUME; \
STM32_USB->CNTR |= USB_CNTR_L2RES; \
osalThreadSleepMilliseconds(STM32_USB_HOST_WAKEUP_DURATION); \
STM32_USB->CNTR &= ~USB_CNTR_RESUME; \
STM32_USB->CNTR &= ~USB_CNTR_L2RES; \
} while (false)
/*===========================================================================*/

2
os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
View File

@ -136,6 +136,8 @@ typedef struct {
#define STM32_USBRAM_BASE USB1_PMAADDR
#elif defined(USB_PMAADDR)
#define STM32_USBRAM_BASE USB_PMAADDR
#elif defined(USB_DRD_PMAADDR)
#define STM32_USBRAM_BASE USB_DRD_PMAADDR
#else
#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000)
#endif

36
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -86,6 +86,9 @@ const halclkcfg_t hal_clkcfg_default = {
#if STM32_HSI16_ENABLED
| RCC_CR_HSIKERON | RCC_CR_HSION
#endif
#if STM32_HSI48_ENABLED
| RCC_CR_HSI48ON
#endif
#if STM32_HSE_ENABLED
| RCC_CR_HSEON
#endif
@ -255,12 +258,25 @@ __STATIC_INLINE void hal_lld_set_static_clocks(void) {
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;
/* CCIPR register initialization, note.*/
RCC->CCIPR = STM32_ADCSEL | STM32_RNGDIV | STM32_RNGSEL |
STM32_TIM15SEL | STM32_TIM1SEL | STM32_LPTIM2SEL |
STM32_LPTIM1SEL | STM32_I2S1SEL | STM32_I2C1SEL |
STM32_CECSEL | STM32_USART2SEL | STM32_USART1SEL |
STM32_LPUART1SEL;
#if STM32_RCC_HAS_CCIPR2
/* CCIPR register initialization.*/
RCC->CCIPR = STM32_ADCSEL | STM32_RNGDIV | STM32_RNGSEL |
STM32_TIM15SEL | STM32_TIM1SEL | STM32_LPTIM2SEL |
STM32_LPTIM1SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_CECSEL | STM32_USART2SEL | STM32_USART1SEL |
STM32_LPUART1SEL;
/* CCIPR2 register initialization.*/
RCC->CCIPR2 = STM32_USBSEL | STM32_FDCANSEL | STM32_I2S2SEL |
STM32_I2S1SEL;
#else
/* CCIPR register initialization.*/
RCC->CCIPR = STM32_ADCSEL | STM32_RNGDIV | STM32_RNGSEL |
STM32_TIM15SEL | STM32_TIM1SEL | STM32_LPTIM2SEL |
STM32_LPTIM1SEL | STM32_I2S1SEL | STM32_I2C1SEL |
STM32_CECSEL | STM32_USART2SEL | STM32_USART1SEL |
STM32_LPUART1SEL;
#endif
}
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
@ -508,6 +524,13 @@ static bool hal_lld_clock_raw_config(const halclkcfg_t *ccp) {
hse_enable();
}
#if STM32_RCC_HAS_HSI48
/* HSI48 setup, if required, before starting the PLL.*/
if ((ccp->rcc_cr & RCC_CR_HSI48ON) != 0U) {
hsi48_enable();
}
#endif
/* PLL setup.*/
RCC->PLLCFGR = ccp->rcc_pllcfgr;
@ -707,6 +730,7 @@ void stm32_clock_init(void) {
lse_init();
lsi_init();
hsi16_init();
hsi48_init();
hse_init();
/* Backup domain initializations.*/

140
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -164,14 +164,19 @@
#define STM32_SW_LSI (3U << 0U) /**< SYSCLK source is LSI. */
#define STM32_SW_LSE (4U << 0U) /**< SYSCLK source is LSE. */
#define STM32_MCOSEL_MASK (7U << 24U) /**< MCOSEL field mask. */
#define STM32_MCOSEL_MASK (15U << 24U)/**< MCOSEL field mask. */
#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
#define STM32_MCOSEL_SYSCLK (1U << 24U) /**< SYSCLK on MCO pin. */
#define STM32_MCOSEL_HSI48 (3U << 24U) /**< HSI48 clock on MCO pin. */
#define STM32_MCOSEL_HSI16 (3U << 24U) /**< HSI16 clock on MCO pin. */
#define STM32_MCOSEL_HSE (4U << 24U) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLRCLK (5U << 24U) /**< PLLR clock on MCO pin. */
#define STM32_MCOSEL_LSI (6U << 24U) /**< LSI clock on MCO pin. */
#define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */
#define STM32_MCOSEL_PLLPCLK (8U << 24U) /**< PLLP clock on MCO pin. */
#define STM32_MCOSEL_PLLQCLK (9U << 24U) /**< PLLQ clock on MCO pin. */
#define STM32_MCOSEL_RTCCLK (10U << 24U)/**< RTC clock on MCO pin. */
#define STM32_MCOSEL_RTCWKP (11U << 24U)/**< RTC WKP clock on MCO pin. */
#define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */
#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */
@ -226,11 +231,18 @@
#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
#if STM32_RCC_HAS_CCIPR2
#define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C1SEL mask. */
#define STM32_I2C2SEL_PCLK (0U << 14U) /**< I2C1 source is PCLK. */
#define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C1 source is SYSCLK. */
#define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C1 source is HSI16. */
#else
#define STM32_I2S1SEL_MASK (3U << 14U) /**< I2S1SEL mask. */
#define STM32_I2S1SEL_SYSCLK (0U << 14U) /**< I2S1 source is SYSCLK. */
#define STM32_I2S1SEL_PLLPCLK (1U << 14U) /**< I2S1 source is PLLPCLK. */
#define STM32_I2S1SEL_HSI16 (2U << 14U) /**< I2S1 source is HSI16. */
#define STM32_I2S1SEL_CKIN (3U << 14U) /**< I2S1 source is CKIN. */
#endif
#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
#define STM32_LPTIM1SEL_PCLK (0U << 18U) /**< LPTIM1 source is PCLK. */
@ -271,6 +283,36 @@
#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
/** @} */
/**
* @name RCC_CCIPR2 register bits definitions
* @{
*/
#if STM32_RCC_HAS_CCIPR2 || defined(__DOXYGEN__)
#define STM32_I2S1SEL_MASK (3U << 0U) /**< I2S1SEL mask. */
#define STM32_I2S1SEL_SYSCLK (0U << 0U) /**< I2S1 source is SYSCLK. */
#define STM32_I2S1SEL_PLLPCLK (1U << 0U) /**< I2S1 source is PLLPCLK. */
#define STM32_I2S1SEL_HSI16 (2U << 0U) /**< I2S1 source is HSI16. */
#define STM32_I2S1SEL_CKIN (3U << 0U) /**< I2S1 source is CKIN. */
#endif /* STM32_RCC_HAS_CCIPR2 */
#define STM32_I2S2SEL_MASK (3U << 2U) /**< I2S2SEL mask. */
#define STM32_I2S2SEL_SYSCLK (0U << 2U) /**< I2S2 source is SYSCLK. */
#define STM32_I2S2SEL_PLLPCLK (1U << 2U) /**< I2S2 source is PLLPCLK. */
#define STM32_I2S2SEL_HSI16 (2U << 2U) /**< I2S2 source is HSI16. */
#define STM32_I2S2SEL_CKIN (3U << 2U) /**< I2S2 source is CKIN. */
#define STM32_FDCANSEL_MASK (3U << 8U) /**< FDCANSEL mask. */
#define STM32_FDCANSEL_PCLK (0U << 8U) /**< FDCANSEL source is PCLK. */
#define STM32_FDCANSEL_PLLQCLK (1U << 8U) /**< FDCANSEL source is PLLQCLK.*/
#define STM32_FDCANSEL_HSE (2U << 8U) /**< FDCANSEL source is HSE. */
#define STM32_USBSEL_MASK (3U << 12U) /**< USBSEL mask. */
#define STM32_USBSEL_HSI48 (0U << 12U) /**< USBSEL source is HSI48. */
#define STM32_USBSEL_PLLQCLK (1U << 12U) /**< USBSEL source is PLLQCLK. */
#define STM32_USBSEL_HSE (2U << 12U) /**< USBSEL source is HSE. */
/** @} */
/**
* @name RCC_BDCR register bits definitions
* @{
@ -483,6 +525,13 @@
#define STM32_HSI16_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSI48 clock source.
*/
#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSI48_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
@ -609,6 +658,20 @@
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#endif
/**
* @brief FDCAN clock source.
*/
#if !defined(STM32_FDCANSEL) || defined(__DOXYGEN__)
#define STM32_FDCANSEL STM32_FDCANSEL_PCLK
#endif
/**
* @brief USB clock source.
*/
#if !defined(STM32_USBSEL) || defined(__DOXYGEN__)
#define STM32_USBSEL STM32_USBSEL_HSI48
#endif
/**
* @brief USART1 clock source.
*/
@ -644,6 +707,13 @@
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
#endif
/**
* @brief I2C2 clock source.
*/
#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK
#endif
/**
* @brief I2S1 clock source.
*/
@ -651,6 +721,13 @@
#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
#endif
/**
* @brief I2S2 clock source.
*/
#if !defined(STM32_I2S2SEL) || defined(__DOXYGEN__)
#define STM32_I2S2SEL STM32_I2S2SEL_SYSCLK
#endif
/**
* @brief LPTIM1 clock source.
*/
@ -915,6 +992,7 @@
#include "stm32_lse.inc"
#include "stm32_lsi.inc"
#include "stm32_hsi16.inc"
#include "stm32_hsi48.inc"
#include "stm32_hse.inc"
/*
@ -935,6 +1013,8 @@
L4 devices.*/
#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
(STM32_I2S1SEL == STM32_I2S1SEL_HSI16) || \
(STM32_I2S2SEL == STM32_I2S2SEL_HSI16) || \
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI16))
#error "HSI16 not enabled, required by STM32_MCOSEL"
@ -978,6 +1058,24 @@
#endif /* !STM32_HSI16_ENABLED */
/*
* HSI48 related checks.
*/
#if STM32_RCC_HAS_HSI48
#if STM32_HSI48_ENABLED
#else /* !STM32_HSI48_ENABLED */
#if STM32_MCOSEL == STM32_MCOSEL_HSI48
#error "HSI48 not enabled, required by STM32_MCOSEL"
#endif
#if (STM32_USBSEL == STM32_USBSEL_HSI48) && (HAL_USE_USB == TRUE)
#error "HSI48 not enabled, required by STM32_USBSEL"
#endif
#endif /* !STM32_HSI48_ENABLED */
#endif /* STM32_RCC_HAS_HSI48 */
/*
* HSE related checks.
*/
@ -993,6 +1091,8 @@
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
(STM32_FDCANSEL == STM32_FDCANSEL_HSE) || \
(STM32_USBSEL == STM32_USBSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
@ -1101,6 +1201,9 @@
(STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
(STM32_I2S2SEL == STM32_I2S2SEL_PLLPCLK) || \
(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
(STM32_USBSEL == STM32_USBSEL_PLLQCLK) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
@ -1128,6 +1231,8 @@
#if (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \
(STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \
(STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
(STM32_USBSEL == STM32_USBSEL_PLLQCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLQEN (1 << 24)
#else
@ -1139,6 +1244,7 @@
*/
#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
(STM32_I2S2SEL == STM32_I2S2SEL_PLLPCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLPEN (1 << 16)
#else
@ -1525,6 +1631,38 @@
*/
#define STM32_TIMCLK2 hal_lld_get_clock_point(CLK_PCLKTIM)
/**
* @brief FDCAN clock point.
*/
#if (STM32_FDCANSEL == STM32_FDCANSEL_PCLK) || defined(__DOXYGEN__)
#define STM32_FDCANCLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK
#define STM32_FDCANCLK hal_lld_get_clock_point(CLK_PLLQCLK)
#elif STM32_FDCANSEL == STM32_FDCANSEL_HSE
#define STM32_FDCANCLK STM32_HSECLK
#else
#error "invalid source selected for FDCAN clock"
#endif
/**
* @brief USB clock point.
*/
#if (STM32_USBSEL == STM32_USBSEL_HSI48) || defined(__DOXYGEN__)
#define STM32_USBCLK STM32_HSI48CLK
#elif STM32_USBSEL == STM32_USBSEL_PLLQCLK
#define STM32_USBCLK hal_lld_get_clock_point(CLK_PLLQCLK)
#elif STM32_USBSEL == STM32_USBSEL_HSE
#define STM32_USBCLK STM32_HSECLK
#else
#error "invalid source selected for USB clock"
#endif
/**
* @brief Flash settings.
*/

1
os/hal/ports/STM32/STM32G0xx/platform.mk
View File

@ -39,6 +39,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
# Shared variables

8
os/hal/ports/STM32/STM32G0xx/stm32_isr.h
View File

@ -170,6 +170,14 @@
#define STM32_LPUART1_NUMBER 29
#define STM32_USART3_4_LP1_NUMBER STM32_LPUART1_NUMBER
#define STM32_USART3_4_5_6_LP1_NUMBER STM32_LPUART1_NUMBER
/*
* USB units.
*/
#define STM32_USB1_HP_HANDLER Vector60
#define STM32_USB1_LP_HANDLER Vector60
#define STM32_USB1_HP_NUMBER 8
#define STM32_USB1_LP_NUMBER 8
/** @} */
/*===========================================================================*/

9
os/hal/ports/STM32/STM32G0xx/stm32_registry.h
View File

@ -87,7 +87,6 @@
/* RCC attributes (common).*/
#define STM32_RCC_HAS_HSI16 TRUE
#define STM32_RCC_HAS_HSI48 FALSE
#define STM32_RCC_HAS_MSI FALSE
#define STM32_RCC_HAS_LSI TRUE
#define STM32_RCC_HAS_LSI_PRESCALER FALSE
@ -179,7 +178,9 @@
#define STM32_HAS_QUADSPI1 FALSE
/* RCC attributes.*/
#define STM32_RCC_HAS_HSI48 FALSE
#define STM32_RCC_PLL_HAS_Q FALSE
#define STM32_RCC_HAS_CCIPR2 FALSE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE
@ -364,7 +365,9 @@
#define STM32_HAS_QUADSPI1 FALSE
/* RCC attributes.*/
#define STM32_RCC_HAS_HSI48 FALSE
#define STM32_RCC_PLL_HAS_Q TRUE
#define STM32_RCC_HAS_CCIPR2 FALSE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE
@ -542,7 +545,9 @@
#define STM32_HAS_QUADSPI1 FALSE
/* RCC attributes.*/
#define STM32_RCC_HAS_HSI48 FALSE
#define STM32_RCC_PLL_HAS_Q TRUE
#define STM32_RCC_HAS_CCIPR2 FALSE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE
@ -731,7 +736,9 @@
#define STM32_HAS_QUADSPI1 FALSE
/* RCC attributes.*/
#define STM32_RCC_HAS_HSI48 TRUE
#define STM32_RCC_PLL_HAS_Q TRUE
#define STM32_RCC_HAS_CCIPR2 TRUE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE

6
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -1015,10 +1015,10 @@
#error "HSI16 not enabled, required by STM32_USART3SEL"
#endif
#if (STM32_UART4SEL == STM32_UART4SEL_HSI16)
#error "HSI16 not enabled, required by STM32_UART4SEL_HSI16"
#error "HSI16 not enabled, required by STM32_UART4SEL"
#endif
#if (STM32_UART5SEL == STM32_UART5SEL_HSI16)
#error "HSI16 not enabled, required by STM32_UART5SEL_HSI16"
#error "HSI16 not enabled, required by STM32_UART5SEL"
#endif
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_LPUART1SEL"
@ -1049,7 +1049,7 @@
#endif
#if (STM32_QSPISEL == STM32_QSPISEL_HSI16)
#error "HSI16 not enabled, required by STM32_QSPISEL_HSI16"
#error "HSI16 not enabled, required by STM32_QSPISEL"
#endif
#endif /* !STM32_HSI16_ENABLED */