Added platform files for ADUCM41x (still incomplete)
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13412 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Rocco Marco Guglielmi
parent
1cdf530014
commit
6e87db625b
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/*
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ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADUCM36x/aducm_gp.h
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* @brief ADUCM GP units common header.
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* @note This file requires definitions from the ADI ADUCM header file.
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*
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* @{
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*/
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#ifndef ADUCM_GP_H
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#define ADUCM_GP_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name GP ports definitions
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* @{
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*/
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#define GP0 ((aducm_gp_t *)pADI_GPIO0)
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#define GP1 ((aducm_gp_t *)pADI_GPIO1)
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#define GP2 ((aducm_gp_t *)pADI_GPIO2)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADUCM36x GPIO registers block.
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*/
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typedef struct {
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volatile uint32_t CON;
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volatile uint32_t OEN;
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volatile uint32_t PUL;
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volatile uint32_t OCE;
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volatile uint32_t RES0;
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volatile uint32_t IN;
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volatile uint32_t OUT;
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volatile uint32_t SET;
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volatile uint32_t CLR;
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volatile uint32_t TGL;
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} aducm_gp_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#endif /* ADUCM_GP_H */
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/** @} */
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@ -0,0 +1,69 @@
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/*
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ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADUCM36x/ADUCM_isr.h
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* @brief ADUCM36x ISR handler code.
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*
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* @addtogroup ADUCM36x_ISR
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Enables IRQ sources.
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*
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* @notapi
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*/
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void irqInit(void) {
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}
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/**
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* @brief Disables IRQ sources.
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*
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* @notapi
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*/
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void irqDeinit(void) {
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}
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/** @} */
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@ -0,0 +1,98 @@
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/*
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ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADUCM41x/aducm_isr.h
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* @brief ADUCM41x ISR handler header.
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*
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* @addtogroup ADUCM41x_ISR
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* @{
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*/
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#ifndef ADUCM_ISR_H
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#define ADUCM_ISR_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* SPI units.
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*/
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#define ADUCM_SPI0_HANDLER Vector88
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#define ADUCM_SPI1_HANDLER Vector8C
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#define ADUCM_SPI0_NUMBER 18
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#define ADUCM_SPI1_NUMBER 19
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/*
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* TIM units.
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*/
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#define ADUCM_TIMER0_HANDLER Vector6C
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#define ADUCM_TIMER1_HANDLER Vector70
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#define ADUCM_TIMER2_HANDLER Vector40
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#define ADUCM_TIMER3_HANDLER Vector64
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#define ADUCM_TIMER0_NUMBER 11
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#define ADUCM_TIMER1_NUMBER 12
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#define ADUCM_TIMER2_NUMBER 0
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#define ADUCM_TIMER3_NUMBER 9
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/*
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* UART units.
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*/
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#define ADUCM_UART0_HANDLER Vector84
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#define ADUCM_UART0_NUMBER 17
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void irqInit(void);
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void irqDeinit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ADUCM_ISR_H */
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/** @} */
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@ -0,0 +1,133 @@
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/*
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ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADUCM41x/hal_lld.c
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* @brief ADUCM41x HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief Reset value of the CLKCON0 register.
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*/
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#define ADUCM_CLKCON0_RESET 0x043CU
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/**
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* @brief Reset value of the CLKCON0 register.
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*/
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#define ADUCM_CLKCON1_RESET 0x0048U
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief CMSIS system core clock variable.
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* @note It is declared in system_ADuCM41x.h.
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*/
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uint32_t SystemCoreClock = ADUCM_HCLK;
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* DMA subsystems initialization.*/
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#if defined(ADUCM_DMA_REQUIRED)
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dmaInit();
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#endif
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/* IRQ subsystem initialization.*/
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irqInit();
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/* Disabling Watchdog timer which is enabled by default. */
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#if HAL_CFG_DISABLE_WDG
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pADI_WDT->CON = 0;
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#endif
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}
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/**
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* @brief ADUCM clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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void aducm_clock_init(void) {
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#if !ADUCM_NO_INIT
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/* Switching the clock source to the internal oscillator. */
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pADI_CLK->CLKCON0 = ADUCM_CLKMUX_HFOSC;
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/* Configuring the clock sources. */
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pADI_CLK->CLKCON0 |= ADUCM_CLKOUT | ADUCM_AMUX | ADUCM_ANAROOT;
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/* Managing the clock dividers. */
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pADI_CLK->CLKCON1 = ADUCM_CDHCLK_DIV | ADUCM_CDPCLK0_DIV |
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ADUCM_CDPCLK1_DIV | ADUCM_CDANACLK_DIV;
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#if((ADUCM_CLKMUX == ADUCM_CLKMUX_SPLL) || \
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(ADUCM_CLKOUT == ADUCM_CLKOUT_SPLL) || \
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(ADUCM_ANAROOT == ADUCM_ANAROOT_SPLL))
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/* Enabling PLL auto-gate.*/
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pADI_PLL->PLLPDCTRL |= BITM_PLL_MMRS_PLLPDCTRL_TOTPDB;
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#endif
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/* Changing the clock source. Note that the field is already zeroed by the
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previous configuration. */
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pADI_CLK->CLKCON0 |= ADUCM_CLKMUX;
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#if((ADUCM_CLKMUX == ADUCM_CLKMUX_SPLL) || \
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(ADUCM_CLKOUT == ADUCM_CLKOUT_SPLL) || \
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(ADUCM_ANAROOT == ADUCM_ANAROOT_SPLL))
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/* Waits until the SPLL is stable */
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while ((pADI_CLK->CLKSTAT0 & ADUCM_SPLL_STA_MASK) == ADUCM_SPLL_STA_UNLOCKED)
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;
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#endif
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#endif /* !ADUCM_NO_INIT */
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}
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/** @} */
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@ -0,0 +1,436 @@
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/*
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ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
|
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You may obtain a copy of the License at
|
||||
|
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http://www.apache.org/licenses/LICENSE-2.0
|
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|
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Unless required by applicable law or agreed to in writing, software
|
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distributed under the License is distributed on an "AS IS" BASIS,
|
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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See the License for the specific language governing permissions and
|
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limitations under the License.
|
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*/
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/**
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* @file ADUCM41x/hal_lld.h
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* @brief ADUCM41x HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - ADUCM_LFXTAL.
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* .
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* One of the following macros must also be defined:
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* - ADUCM410.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef HAL_LLD_H
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#define HAL_LLD_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Platform identification macros
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* @{
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*/
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#if defined(ADUCM410) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "ADUCM410 Precision Analog MCU with 16-bit MDIO interface"
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#else
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#error "ADUCM41x device unsupported or not specified"
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#endif
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/** @} */
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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#if defined(ADUCM410) || defined(__DOXYGEN__)
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/**
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* @brief Absolute maximum external clock.
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*/
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#define ADUCM_EXTCLK_MAX 32000000
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/**
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* @brief Absolute minimum external clock.
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*/
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#define ADUCM_EXTCLK_MIN 16000000
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/**
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* @brief Absolute maximum external clock.
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*/
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#define ADUCM_AFE_CLK_MAX 32000000
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/**
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* @brief Absolute minimum external clock.
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*/
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#define ADUCM_AFE_CLK_MIN 32000000
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#endif
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define ADUCM_HFOSC 16000000 /**< High speed internal clock. */
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#define ADUCM_SPLL 160000000 /**< System PLL clock. */
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#define ADUCM_LFOSC 32768 /**< Low speed internal clock. */
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/** @} */
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/**
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* @name CLKCON0 register bits definitions
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* @{
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*/
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#define ADUCM_CLKMUX_HFOSC (0 << 0) /**< Clock source is HFOSC. */
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#define ADUCM_CLKMUX_SPLL (1 << 0) /**< Clock source is SPLL. */
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#define ADUCM_CLKMUX_EXTCLK (3 << 0) /**< Clock source is EXTCLK. */
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#define ADUCM_CLKOUT_HFOSC (0 << 2) /**< Clock out 16 MHz. */
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#define ADUCM_CLKOUT_ROOTCLK (1 << 2) /**< Clock out Root Clock. */
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#define ADUCM_CLKOUT_LFOSC (3 << 2) /**< Clock out 32 KHz. */
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#define ADUCM_CLKOUT_CORECLK (4 << 2) /**< Clock out Core Clock. */
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#define ADUCM_CLKOUT_PCLK0 (5 << 2) /**< Clock out Periph. Clock 0. */
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#define ADUCM_CLKOUT_PCLK1 (6 << 2) /**< Clock out Periph. Clock 1. */
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#define ADUCM_CLKOUT_PCLK2 (7 << 2) /**< Clock out Periph. Clock 2. */
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#define ADUCM_CLKOUT_ATS (8 << 2) /**< Clock out Analog Test Sign.*/
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#define ADUCM_CLKOUT_T0 (9 << 2) /**< Clock out Timer 0. */
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#define ADUCM_CLKOUT_WUT (10 << 2) /**< Clock out Wake-up Timer. */
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#define ADUCM_CLKOUT_T3 (11 << 2) /**< Clock out Timer 3. */
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#define ADUCM_CLKOUT_HCLK (12 << 2) /**< Clock out HCLK. */
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#define ADUCM_CLKOUT_SPLL (13 << 2) /**< Clock out System PLL. */
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#define ADUCM_CLKOUT_DISABLED (15 << 2) /**< Clock out Disabled. */
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#define ADUCM_AMUX_HFOSC (0 << 7) /**< AMux is 16 MHz. */
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#define ADUCM_AMUX_EXTCLK (2 << 7) /**< AMux is EXTCLK. */
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#define ADUCM_SPLLIE_ENABLED (1 << 9) /**< PLL Lock/Unlock IRQ en. */
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#define ADUCM_SPLLIE_DISABLED (0 << 9) /**< PLL Lock/Unlock IRQ dis. */
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#define ADUCM_ANAROOT_AMUX (0 << 10) /**< Analog clock is AMux. */
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#define ADUCM_ANAROOT_AMUX_X2 (1 << 10) /**< Analog clock is AMux x 2. */
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#define ADUCM_ANAROOT_SPLL (2 << 10) /**< Analog clock is System PLL.*/
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#define ADUCM_ANAROOT_EXTCLK (3 << 10) /**< Analog clock is EXTCLK. */
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/** @} */
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/**
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* @name CLKCON1 register bits definitions
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* @{
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*/
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#define ADUCM_CDHCLK_DIV1 (0 << 0) /**< HCLK divided by 1. */
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#define ADUCM_CDHCLK_DIV2 (1 << 0) /**< HCLK divided by 2. */
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||||
#define ADUCM_CDHCLK_DIV4 (2 << 0) /**< HCLK divided by 4. */
|
||||
#define ADUCM_CDHCLK_DIV8 (3 << 0) /**< HCLK divided by 8. */
|
||||
#define ADUCM_CDHCLK_DIV16 (4 << 0) /**< HCLK divided by 16. */
|
||||
#define ADUCM_CDHCLK_DIV32 (5 << 0) /**< HCLK divided by 32. */
|
||||
#define ADUCM_CDHCLK_DIV64 (6 << 0) /**< HCLK divided by 64. */
|
||||
#define ADUCM_CDHCLK_DIV128 (7 << 0) /**< HCLK divided by 128. */
|
||||
|
||||
#define ADUCM_CDPCLK0_DIV1 (0 << 3) /**< PCLK0 divided by 1. */
|
||||
#define ADUCM_CDPCLK0_DIV2 (1 << 3) /**< PCLK0 divided by 2. */
|
||||
#define ADUCM_CDPCLK0_DIV4 (2 << 3) /**< PCLK0 divided by 4. */
|
||||
#define ADUCM_CDPCLK0_DIV8 (3 << 3) /**< PCLK0 divided by 8. */
|
||||
#define ADUCM_CDPCLK0_DIV16 (4 << 3) /**< PCLK0 divided by 16. */
|
||||
#define ADUCM_CDPCLK0_DIV32 (5 << 3) /**< PCLK0 divided by 32. */
|
||||
#define ADUCM_CDPCLK0_DIV64 (6 << 3) /**< PCLK0 divided by 64. */
|
||||
#define ADUCM_CDPCLK0_DIV128 (7 << 3) /**< PCLK0 divided by 128. */
|
||||
|
||||
#define ADUCM_CDPCLK1_DIV1 (0 << 6) /**< PCLK1 divided by 1. */
|
||||
#define ADUCM_CDPCLK1_DIV2 (1 << 6) /**< PCLK1 divided by 2. */
|
||||
#define ADUCM_CDPCLK1_DIV4 (2 << 6) /**< PCLK1 divided by 4. */
|
||||
#define ADUCM_CDPCLK1_DIV8 (3 << 6) /**< PCLK1 divided by 8. */
|
||||
#define ADUCM_CDPCLK1_DIV16 (4 << 6) /**< PCLK1 divided by 16. */
|
||||
#define ADUCM_CDPCLK1_DIV32 (5 << 6) /**< PCLK1 divided by 32. */
|
||||
#define ADUCM_CDPCLK1_DIV64 (6 << 6) /**< PCLK1 divided by 64. */
|
||||
#define ADUCM_CDPCLK1_DIV128 (7 << 6) /**< PCLK1 divided by 128. */
|
||||
|
||||
#define ADUCM_CDANACLK_DIV1 (0 << 9) /**< Analog FE divided by 1. */
|
||||
#define ADUCM_CDANACLK_DIV2 (1 << 9) /**< Analog FE divided by 2. */
|
||||
#define ADUCM_CDANACLK_DIV4 (2 << 9) /**< Analog FE divided by 4. */
|
||||
#define ADUCM_CDANACLK_DIV8 (3 << 9) /**< Analog FE divided by 8. */
|
||||
#define ADUCM_CDANACLK_DIV16 (4 << 9) /**< Analog FE divided by 16. */
|
||||
#define ADUCM_CDANACLK_DIV32 (5 << 9) /**< Analog FE divided by 32. */
|
||||
#define ADUCM_CDANACLK_DIV64 (6 << 9) /**< Analog FE divided by 64. */
|
||||
#define ADUCM_CDANACLK_DIV128 (7 << 9) /**< Analog FE divided by 128. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CLKSTAT0 register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define ADUCM_SPLL_STA_MASK 0x0001 /**< System PLL status mask. */
|
||||
#define ADUCM_SPLL_STA_UNLOCKED (0 << 0) /**< System PLL locked. */
|
||||
#define ADUCM_SPLL_STA_LOCKED (1 << 0) /**< System PLL unlocked. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Disables the CA initialization in the HAL.
|
||||
*/
|
||||
#if !defined(ADUCM_NO_INIT) || defined(__DOXYGEN__)
|
||||
#define ADUCM_NO_INIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Main clock source selection.
|
||||
*/
|
||||
#if !defined(ADUCM_CLKMUX) || defined(__DOXYGEN__)
|
||||
#define ADUCM_CLKMUX ADUCM_CLKMUX_SPLL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock out source selection.
|
||||
*/
|
||||
#if !defined(ADUCM_CLKOUT) || defined(__DOXYGEN__)
|
||||
#define ADUCM_CLKOUT ADUCM_CLKOUT_DISABLED
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Analog clock multiplexer selection.
|
||||
*/
|
||||
#if !defined(ADUCM_AMUX) || defined(__DOXYGEN__)
|
||||
#define ADUCM_AMUX ADUCM_AMUX_HFOSC
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Analog clock root source.
|
||||
*/
|
||||
#if !defined(ADUCM_ANAROOT) || defined(__DOXYGEN__)
|
||||
#define ADUCM_ANAROOT ADUCM_ANAROOT_AMUX_X2
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief High Speed Bus clock divider.
|
||||
*/
|
||||
#if !defined(ADUCM_CDHCLK_DIV) || defined(__DOXYGEN__)
|
||||
#define ADUCM_CDHCLK_DIV ADUCM_CDHCLK_DIV1
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Peripheral Bus 0 clock divider.
|
||||
*/
|
||||
#if !defined(ADUCM_CDPCLK0_DIV) || defined(__DOXYGEN__)
|
||||
#define ADUCM_CDPCLK0_DIV ADUCM_CDPCLK0_DIV1
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Peripheral Bus 1 clock divider.
|
||||
*/
|
||||
#if !defined(ADUCM_CDPCLK1_DIV) || defined(__DOXYGEN__)
|
||||
#define ADUCM_CDPCLK1_DIV ADUCM_CDPCLK1_DIV1
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief ADC clock divider.
|
||||
*/
|
||||
#if !defined(ADUCM_CDANACLK_DIV) || defined(__DOXYGEN__)
|
||||
#define ADUCM_CDANACLK_DIV ADUCM_CDANACLK_DIV1
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(ADUCM41x_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, ADUCM41x_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SYSCLK source.
|
||||
*/
|
||||
#if (ADUCM_CLKMUX == ADUCM_CLKMUX_HFOSC) || defined(__DOXYGEN__)
|
||||
#define ADUCM_SYSCLK ADUCM_HFOSC
|
||||
#elif ADUCM_CLKMUX == ADUCM_CLKMUX_SPLL
|
||||
#define ADUCM_SYSCLK ADUCM_SPLL
|
||||
#elif ADUCM_CLKMUX == ADUCM_CLKMUX_EXTCLK
|
||||
#define ADUCM_SYSCLK ADUCM_EXTCLK
|
||||
#else
|
||||
#error "invalid ADUCM_CLKMUX value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AMUX source.
|
||||
*/
|
||||
#if (ADUCM_AMUX == ADUCM_AMUX_HFOSC) || defined(__DOXYGEN__)
|
||||
#define ADUCM_AMUX_CLK ADUCM_HFOSC
|
||||
#elif ADUCM_ANAROOT == ADUCM_ANAROOT_EXTCLK
|
||||
#define ADUCM_AMUX_CLK ADUCM_EXTCLK
|
||||
#else
|
||||
#error "invalid ADUCM_AMUX value specified"
|
||||
#endif
|
||||
|
||||
#if (ADUCM_CLKMUX == ADUCM_CLKMUX_EXTCLK) || (ADUCM_ANAROOT == ADUCM_ANAROOT_EXTCLK)
|
||||
|
||||
/* External clock frequency check.*/
|
||||
#if (ADUCM_EXTCLK < ADUCM_EXTCLK_MIN) || (ADUCM_EXTCLK > ADUCM_EXTCLK_MAX)
|
||||
#error "ADUCM_EXTCLK outside acceptable range (ADUCM_EXTCLK_MIN...ADUCM_EXTCLK_MAX)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ANAROOT source.
|
||||
*/
|
||||
#if (ADUCM_ANAROOT == ADUCM_ANAROOT_AMUX) || defined(__DOXYGEN__)
|
||||
#define ADUCM_ANAROOT_CLK ADUCM_AMUX_CLK
|
||||
#elif ADUCM_ANAROOT == ADUCM_ANAROOT_AMUX_X2
|
||||
#define ADUCM_ANAROOT_CLK (ADUCM_AMUX_CLK * 2)
|
||||
#elif ADUCM_ANAROOT == ADUCM_ANAROOT_SPLL
|
||||
#define ADUCM_ANAROOT_CLK ADUCM_SPLL
|
||||
#elif ADUCM_ANAROOT == ADUCM_CLKMUX_EXTCLK
|
||||
#define ADUCM_ANAROOT_CLK ADUCM_EXTCLK
|
||||
#else
|
||||
#error "invalid ADUCM_ANAROOT value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief HCLK frequency.
|
||||
*/
|
||||
#if (ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV1) || defined(__DOXYGEN__)
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 1)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV2
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 2)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV4
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 4)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV8
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 8)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV16
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 16)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV32
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 32)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV64
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 64)
|
||||
#elif ADUCM_CDHCLK_DIV == ADUCM_CDHCLK_DIV128
|
||||
#define ADUCM_HCLK (ADUCM_SYSCLK / 128)
|
||||
#else
|
||||
#error "invalid ADUCM_CDHCLK_DIV value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PCLK0 frequency.
|
||||
*/
|
||||
#if (ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV1) || defined(__DOXYGEN__)
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 1)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV2
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 2)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV4
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 4)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV8
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 8)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV16
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 16)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV32
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 32)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV64
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 64)
|
||||
#elif ADUCM_CDPCLK0_DIV == ADUCM_CDPCLK0_DIV128
|
||||
#define ADUCM_PCLK0 (ADUCM_SYSCLK / 128)
|
||||
#else
|
||||
#error "invalid ADUCM_CDPCLK0_DIV value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PCLK1 frequency.
|
||||
*/
|
||||
#if (ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV1) || defined(__DOXYGEN__)
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 1)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV2
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 2)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV4
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 4)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV8
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 8)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV16
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 16)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV32
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 32)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV64
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 64)
|
||||
#elif ADUCM_CDPCLK1_DIV == ADUCM_CDPCLK1_DIV128
|
||||
#define ADUCM_PCLK1 (ADUCM_SYSCLK / 128)
|
||||
#else
|
||||
#error "invalid ADUCM_CDPCLK1_DIV value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Analog Front End frequency.
|
||||
*/
|
||||
#if (ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV1) || defined(__DOXYGEN__)
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 1)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV2
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 2)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV4
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 4)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV8
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 8)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV16
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 16)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV32
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 32)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANACLK_DIV64
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 64)
|
||||
#elif ADUCM_CDANACLK_DIV == ADUCM_CDANA_DIV128
|
||||
#define ADUCM_AFE_CLK (ADUCM_ANAROOT_CLK / 128)
|
||||
#else
|
||||
#error "invalid ADUCM_CDANA_DIV value specified"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Analog Front End clock check.
|
||||
*/
|
||||
#if (ADUCM_AFE_CLK < ADUCM_AFE_CLK_MIN) || (ADUCM_AFE_CLK > ADUCM_AFE_CLK_MAX)
|
||||
#warning "The AFE is calibrated to work with a 32MHz clock."
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* Various helpers.*/
|
||||
#include "nvic.h"
|
||||
#include "cache.h"
|
||||
#include "aducm_isr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hal_lld_init(void);
|
||||
void aducm_clock_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_LLD_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ADUCM36x/hal_st_lld.c
|
||||
* @brief ST Driver subsystem low level driver code.
|
||||
*
|
||||
* @addtogroup ST
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
|
||||
|
||||
#define SYSTICK_CK ADUCM_HCLK
|
||||
|
||||
#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0
|
||||
#error "the selected ST frequency is not obtainable because integer rounding"
|
||||
#endif
|
||||
|
||||
#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF
|
||||
#error "the selected ST frequency is not obtainable because SysTick timer counter limits"
|
||||
#endif
|
||||
|
||||
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief System Timer vector.
|
||||
* @details This interrupt is used for system tick in periodic mode.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(SysTick_Handler) {
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
osalSysLockFromISR();
|
||||
osalOsTimerHandlerI();
|
||||
osalSysUnlockFromISR();
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level ST driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void st_lld_init(void) {
|
||||
|
||||
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
|
||||
/* Periodic systick mode, the Cortex-Mx internal systick timer is used
|
||||
in this mode.*/
|
||||
SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1;
|
||||
SysTick->VAL = 0;
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
/* IRQ enabled.*/
|
||||
nvicSetSystemHandlerPriority(HANDLER_SYSTICK, ADUCM_ST_IRQ_PRIORITY);
|
||||
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
|
||||
}
|
||||
|
||||
#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ADUCM41x/hal_st_lld.h
|
||||
* @brief ST Driver subsystem low level driver header.
|
||||
* @details This header is designed to be include-able without having to
|
||||
* include other files from the HAL.
|
||||
*
|
||||
* @addtogroup ST
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HAL_ST_LLD_H
|
||||
#define HAL_ST_LLD_H
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief SysTick timer IRQ priority.
|
||||
*/
|
||||
#if !defined(ADUCM_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define ADUCM_ST_IRQ_PRIORITY 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMx unit (by number) to be used for free running operations.
|
||||
* @note You must select a 32 bits timer if a 32 bits @p systick_t type
|
||||
* is required.
|
||||
* @note Timers 0, 1, 2 are supported.
|
||||
*/
|
||||
#if !defined(ADUCM_ST_USE_TIMER) || defined(__DOXYGEN__)
|
||||
#define ADUCM_ST_USE_TIMER 2
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)
|
||||
#error "Tickless mode still not supported on this platform."
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void st_lld_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver inline functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Returns the time counter value.
|
||||
*
|
||||
* @return The counter value.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
static inline systime_t st_lld_get_counter(void) {
|
||||
|
||||
return (systime_t)0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the alarm.
|
||||
* @note Makes sure that no spurious alarms are triggered after
|
||||
* this call.
|
||||
*
|
||||
* @param[in] abstime the time to be set for the first alarm
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
static inline void st_lld_start_alarm(systime_t abstime) {
|
||||
(void) abstime;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the alarm interrupt.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
static inline void st_lld_stop_alarm(void) {
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the alarm time.
|
||||
*
|
||||
* @param[in] abstime the time to be set for the next alarm
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
static inline void st_lld_set_alarm(systime_t abstime) {
|
||||
(void) abstime;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current alarm time.
|
||||
*
|
||||
* @return The currently set alarm time.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
static inline systime_t st_lld_get_alarm(void) {
|
||||
|
||||
return (systime_t)0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Determines if the alarm is active.
|
||||
*
|
||||
* @return The alarm status.
|
||||
* @retval false if the alarm is not active.
|
||||
* @retval true is the alarm is active
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
static inline bool st_lld_is_alarm_active(void) {
|
||||
|
||||
return (bool)(0);
|
||||
}
|
||||
#endif /* HAL_ST_LLD_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Required platform files.
|
||||
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM41x/aducm_isr.c \
|
||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM41x/hal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM41x/hal_st_lld.c
|
||||
|
||||
# Required include directories.
|
||||
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM41x
|
||||
|
||||
# Optional platform files.
|
||||
ifeq ($(USE_SMART_BUILD),yes)
|
||||
|
||||
# Configuration files directory
|
||||
ifeq ($(HALCONFDIR),)
|
||||
ifeq ($(CONFDIR),)
|
||||
HALCONFDIR = .
|
||||
else
|
||||
HALCONFDIR := $(CONFDIR)
|
||||
endif
|
||||
endif
|
||||
|
||||
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
|
||||
|
||||
else
|
||||
endif
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(PLATFORMSRC)
|
||||
ALLINC += $(PLATFORMINC)
|
||||
Loading…
Reference in New Issue