Moved VTOS initialization in startup files.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9364 35acf78f-673a-0410-8e92-d51de3d6d3f4

demos/STM32/RT-STM32F746G-DISCOVERY/chconf.h

@@ -515,8 +515,6 @@
 /* Port-specific settings (override port settings defaulted in chcore.h).    */
 /*===========================================================================*/
 
-#define CORTEX_VTOR_INIT                    0x00200000U
-
 #endif  /* CHCONF_H */
 
 /** @} */

os/common/ports/ARMCMx/chcore_v7m.h

@@ -150,13 +150,6 @@
 #error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
 #endif
 
-/**
- * @brief   NVIC VTOR initialization expression.
- */
-#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
-#define CORTEX_VTOR_INIT                0x00000000U
-#endif
-
 /**
  * @brief   NVIC PRIGROUP initialization expression.
  * @details The default assigns all available priority bits as preemption
@@ -512,9 +505,6 @@ extern "C" {
  */
 static inline void port_init(void) {
 
-  /* Initialization of the vector table and priority related settings.*/
-  SCB->VTOR = CORTEX_VTOR_INIT;
-
   /* Initializing priority grouping.*/
   NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
 

os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S

@@ -39,10 +39,21 @@
 #define CONTROL_USE_MSP                     0
 #define CONTROL_USE_PSP                     2
 
+#define SCB_VTOR                            0xE000ED08
+
 /*===========================================================================*/
 /* Module pre-compile time settings.                                         */
 /*===========================================================================*/
 
+/**
+ * @brief   VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ * @note    This option can only be enabled on Cortex-M0+ cores.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_VTOR_INIT                      FALSE
+#endif
+
 /**
  * @brief   Control special register initialization value.
  * @details The system is setup to run in privileged mode using the PSP
@@ -140,6 +151,12 @@ Reset_Handler:
                 msr     CONTROL, r0
                 isb
 
+#if CRT0_VTOR_INIT == TRUE
+                ldr     r0, =_vectors
+                ldr     r1, =SCB_VTOR
+                str     r0, [r1]
+#endif
+
 #if CRT0_INIT_CORE == TRUE
                 /* Core initialization.*/
                 bl      __core_init

os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S

@@ -43,6 +43,7 @@
 #define FPCCR_ASPEN                         (1 << 31)
 #define FPCCR_LSPEN                         (1 << 30)
 
+#define SCB_VTOR                            0xE000ED08
 #define SCB_CPACR                           0xE000ED88
 #define SCB_FPCCR                           0xE000EF34
 #define SCB_FPDSCR                          0xE000EF3C
@@ -51,6 +52,14 @@
 /* Module pre-compile time settings.                                         */
 /*===========================================================================*/
 
+/**
+ * @brief   VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_VTOR_INIT                      TRUE
+#endif
+
 /**
  * @brief   FPU initialization switch.
  */
@@ -175,6 +184,13 @@ Reset_Handler:
                 ldr     r0, =__process_stack_end__
                 msr     PSP, r0
 
+#if CRT0_VTOR_INIT == TRUE
+                ldr     r0, =_vectors
+                movw    r1, #SCB_VTOR & 0xFFFF
+                movt    r1, #SCB_VTOR >> 16
+                str     r0, [r1]
+#endif
+
 #if CRT0_INIT_FPU == TRUE
                 /* FPU FPCCR initialization.*/
                 movw    r0, #CRT0_FPCCR_INIT & 0xFFFF

readme.txt

@@ -79,6 +79,8 @@
 *****************************************************************************
 
 *** Next ***
+- VAR: Cortex-M VTOR initialization is now performed in startup files and
+       no more in port initialization.
 - VAR: Changed GCC asm files extension from .s to .S because conventions.
 - VAR: Updated CMSIS to version 4.50, it still contains the same errors
        found in 4.30, fixes applied.