Moved VTOS initialization in startup files.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9364 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -515,8 +515,6 @@
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/* Port-specific settings (override port settings defaulted in chcore.h). */
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/* Port-specific settings (override port settings defaulted in chcore.h). */
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/*===========================================================================*/
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/*===========================================================================*/
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#define CORTEX_VTOR_INIT 0x00200000U
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#endif /* CHCONF_H */
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#endif /* CHCONF_H */
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/** @} */
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/** @} */
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@ -150,13 +150,6 @@
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#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
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#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
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#endif
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#endif
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/**
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* @brief NVIC VTOR initialization expression.
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*/
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#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
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#define CORTEX_VTOR_INIT 0x00000000U
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#endif
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/**
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/**
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* @brief NVIC PRIGROUP initialization expression.
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* @brief NVIC PRIGROUP initialization expression.
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* @details The default assigns all available priority bits as preemption
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* @details The default assigns all available priority bits as preemption
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@ -512,9 +505,6 @@ extern "C" {
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*/
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*/
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static inline void port_init(void) {
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static inline void port_init(void) {
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/* Initialization of the vector table and priority related settings.*/
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SCB->VTOR = CORTEX_VTOR_INIT;
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/* Initializing priority grouping.*/
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/* Initializing priority grouping.*/
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NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
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NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
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@ -39,10 +39,21 @@
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#define CONTROL_USE_MSP 0
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#define CONTROL_USE_MSP 0
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#define CONTROL_USE_PSP 2
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#define CONTROL_USE_PSP 2
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#define SCB_VTOR 0xE000ED08
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief VTOR special register initialization.
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* @details VTOR is initialized to point to the vectors table.
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* @note This option can only be enabled on Cortex-M0+ cores.
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*/
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#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
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#define CRT0_VTOR_INIT FALSE
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#endif
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/**
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/**
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* @brief Control special register initialization value.
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* @brief Control special register initialization value.
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* @details The system is setup to run in privileged mode using the PSP
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* @details The system is setup to run in privileged mode using the PSP
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@ -140,6 +151,12 @@ Reset_Handler:
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msr CONTROL, r0
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msr CONTROL, r0
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isb
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isb
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#if CRT0_VTOR_INIT == TRUE
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ldr r0, =_vectors
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ldr r1, =SCB_VTOR
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str r0, [r1]
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#endif
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#if CRT0_INIT_CORE == TRUE
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#if CRT0_INIT_CORE == TRUE
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/* Core initialization.*/
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/* Core initialization.*/
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bl __core_init
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bl __core_init
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@ -43,6 +43,7 @@
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#define FPCCR_ASPEN (1 << 31)
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#define FPCCR_ASPEN (1 << 31)
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#define FPCCR_LSPEN (1 << 30)
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#define FPCCR_LSPEN (1 << 30)
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#define SCB_VTOR 0xE000ED08
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#define SCB_CPACR 0xE000ED88
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#define SCB_CPACR 0xE000ED88
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#define SCB_FPCCR 0xE000EF34
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#define SCB_FPCCR 0xE000EF34
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#define SCB_FPDSCR 0xE000EF3C
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#define SCB_FPDSCR 0xE000EF3C
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@ -51,6 +52,14 @@
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/* Module pre-compile time settings. */
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief VTOR special register initialization.
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* @details VTOR is initialized to point to the vectors table.
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*/
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#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
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#define CRT0_VTOR_INIT TRUE
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#endif
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/**
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/**
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* @brief FPU initialization switch.
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* @brief FPU initialization switch.
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*/
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*/
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@ -175,6 +184,13 @@ Reset_Handler:
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ldr r0, =__process_stack_end__
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ldr r0, =__process_stack_end__
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msr PSP, r0
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msr PSP, r0
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#if CRT0_VTOR_INIT == TRUE
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ldr r0, =_vectors
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movw r1, #SCB_VTOR & 0xFFFF
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movt r1, #SCB_VTOR >> 16
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str r0, [r1]
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#endif
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#if CRT0_INIT_FPU == TRUE
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#if CRT0_INIT_FPU == TRUE
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/* FPU FPCCR initialization.*/
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/* FPU FPCCR initialization.*/
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movw r0, #CRT0_FPCCR_INIT & 0xFFFF
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movw r0, #CRT0_FPCCR_INIT & 0xFFFF
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@ -79,6 +79,8 @@
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*****************************************************************************
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*****************************************************************************
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*** Next ***
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*** Next ***
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- VAR: Cortex-M VTOR initialization is now performed in startup files and
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no more in port initialization.
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- VAR: Changed GCC asm files extension from .s to .S because conventions.
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- VAR: Changed GCC asm files extension from .s to .S because conventions.
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- VAR: Updated CMSIS to version 4.50, it still contains the same errors
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- VAR: Updated CMSIS to version 4.50, it still contains the same errors
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found in 4.30, fixes applied.
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found in 4.30, fixes applied.
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