andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4716 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2012-09-27 12:11:57 +00:00
parent cd90ae0dab
commit 6f0d2fed0a
5 changed files with 109 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
boards/GENERIC_SPC560P/board.c
View File

@ -23,7 +23,7 @@
#if HAL_USE_PAL || defined(__DOXYGEN__) #if HAL_USE_PAL || defined(__DOXYGEN__)
/* Initial setup of all defined pads, the list is terminated by a {0, 0}.*/ /* Initial setup of all defined pads, the list is terminated by a {0, 0}.*/
static const spc560p_siul_init_t spc560p_siul_init[] = { static const spc560p_siu_init_t spc560p_siu_init[] = {
{PCR(PD, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, {PCR(PD, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
{PCR(PD, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, {PCR(PD, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
{PCR(PD, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, {PCR(PD, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
@ -36,7 +36,7 @@ static const spc560p_siul_init_t spc560p_siul_init[] = {
}; };
/* Initialization array for the PSMI registers.*/ /* Initialization array for the PSMI registers.*/
static const uint8_t spc560p_padsels_init[SPC5_SIUL_NUM_PADSELS] = { static const uint8_t spc560p_padsels_init[SPC5_SIU_NUM_PADSELS] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 0, 0, 0, 0
@ -48,7 +48,7 @@ static const uint8_t spc560p_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
const PALConfig pal_default_config = const PALConfig pal_default_config =
{ {
PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */ PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
spc560p_siul_init, spc560p_siu_init,
spc560p_padsels_init spc560p_padsels_init
}; };
#endif #endif

2
os/hal/platforms/SPC560Pxx/hal_lld.h
View File

@ -50,7 +50,7 @@
* @name Platform identification * @name Platform identification
* @{ * @{
*/ */
#define PLATFORM_NAME "SPC560Pxx Chassis and Safety" #define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
/** @} */ /** @} */
/** /**

11
os/hal/platforms/SPC560Pxx/spc560p_registry.h
View File

@ -37,11 +37,12 @@
* @name SPC560Pxx capabilities * @name SPC560Pxx capabilities
* @{ * @{
*/ */
/* SIUL attributes.*/ /* SIU/SIUL attributes.*/
#define SPC5_HAS_SIUL TRUE #define SPC5_HAS_SIU FALSE
#define SPC5_SIUL_NUM_PORTS 4 #define SPC5_SIU_SUPPORTS_PORTS TRUE
#define SPC5_SIUL_NUM_PCRS 108 #define SPC5_SIU_NUM_PORTS 4
#define SPC5_SIUL_NUM_PADSELS 36 #define SPC5_SIU_NUM_PCRS 108
#define SPC5_SIU_NUM_PADSELS 36
/** @} */ /** @} */
#endif /* _SPC560P_REGISTRY_H_ */ #endif /* _SPC560P_REGISTRY_H_ */

61
os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c
View File

@ -19,8 +19,8 @@
*/ */
/** /**
* @file SPC5xx/SIUL_v1/pal_lld.c * @file SPC5xx/SIU_v1/pal_lld.c
* @brief SPC5xx SIUL low level driver code. * @brief SPC5xx SIU/SIUL low level driver code.
* *
* @addtogroup PAL * @addtogroup PAL
* @{ * @{
@ -66,11 +66,11 @@ void _pal_lld_init(const PALConfig *config) {
unsigned i; unsigned i;
/* Initialize PCR registers for undefined pads.*/ /* Initialize PCR registers for undefined pads.*/
for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) for (i = 0; i < SPC5_SIU_NUM_PCRS; i++)
SIU.PCR[i].R = config->default_mode; SIU.PCR[i].R = config->default_mode;
/* Initialize PADSEL registers.*/ /* Initialize PADSEL registers.*/
for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++) for (i = 0; i < SPC5_SIU_NUM_PADSELS; i++)
SIU.PSMI[i].R = config->padsels[i]; SIU.PSMI[i].R = config->padsels[i];
/* Initialize PCR registers for defined pads.*/ /* Initialize PCR registers for defined pads.*/
@ -82,6 +82,48 @@ void _pal_lld_init(const PALConfig *config) {
} }
} }
/**
* @brief Reads a group of bits.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @return The group logical states.
*
* @notapi
*/
ioportmask_t _pal_lld_readgroup(ioportid_t port,
ioportmask_t mask,
uint_fast8_t offset) {
(void)port;
(void)mask;
(void)offset;
return 0;
}
/**
* @brief Writes a group of bits.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group width
* are masked.
*
* @notapi
*/
void _pal_lld_writegroup(ioportid_t port,
ioportmask_t mask,
uint_fast8_t offset,
ioportmask_t bits) {
(void)port;
(void)mask;
(void)offset;
(void)bits;
}
/** /**
* @brief Pads mode setup. * @brief Pads mode setup.
* @details This function programs a pads group belonging to the same port * @details This function programs a pads group belonging to the same port
@ -96,9 +138,14 @@ void _pal_lld_init(const PALConfig *config) {
void _pal_lld_setgroupmode(ioportid_t port, void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask, ioportmask_t mask,
iomode_t mode) { iomode_t mode) {
(void)port; unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
(void)mask; ioportmask_t m1 = 0x8000;
(void)mode; while (m1) {
if (mask & m1)
SIU.PCR[pcr_index].R = mode;
m1 >>= 1;
++pcr_index;
}
} }
#endif /* HAL_USE_PAL */ #endif /* HAL_USE_PAL */

83
os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h
View File

@ -19,8 +19,8 @@
*/ */
/** /**
* @file SPC5xx/SIUL_v1//pal_lld.h * @file SPC5xx/SIU_v1//pal_lld.h
* @brief SPC5xx SIUL low level driver header. * @brief SPC5xx SIU/SIUL low level driver header.
* *
* @addtogroup PAL * @addtogroup PAL
* @{ * @{
@ -147,7 +147,7 @@ typedef struct {
uint8_t pcr_index; uint8_t pcr_index;
uint8_t gpdo_value; uint8_t gpdo_value;
iomode_t pcr_value; iomode_t pcr_value;
} spc560p_siul_init_t; } spc560p_siu_init_t;
/** /**
* @brief Generic I/O ports static initializer. * @brief Generic I/O ports static initializer.
@ -160,7 +160,7 @@ typedef struct {
*/ */
typedef struct { typedef struct {
iomode_t default_mode; iomode_t default_mode;
const spc560p_siul_init_t *inits; const spc560p_siu_init_t *inits;
const uint8_t *padsels; const uint8_t *padsels;
} PALConfig; } PALConfig;
@ -203,37 +203,6 @@ typedef struct {
*/ */
#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n))) #define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
/**
* @brief Workaround read port because bad header implementation.
*
* @param[in] port port identifier
* @return The port bits.
*
* @notapi
*/
#define PAL_SIUL_READ_PORT(port) (((volatile uint16_t *)SIU.PGPDI)[port])
/**
* @brief Workaround read latch because bad header implementation.
*
* @param[in] port port identifier
* @return The port bits.
*
* @notapi
*/
#define PAL_SIUL_READ_LATCH(port) (((volatile uint16_t *)SIU.PGPDO)[port])
/**
* @brief Workaround write port because bad header implementation.
*
* @param[in] port port identifier
* @param[in] bits bits to be written on the specified port
*
* @notapi
*/
#define PAL_SIUL_WRITE_PORT(port, bits) \
(((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
/** /**
* @brief Low level PAL subsystem initialization. * @brief Low level PAL subsystem initialization.
* *
@ -243,6 +212,7 @@ typedef struct {
*/ */
#define pal_lld_init(config) _pal_lld_init(config) #define pal_lld_init(config) _pal_lld_init(config)
#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__)
/** /**
* @brief Reads the physical I/O port states. * @brief Reads the physical I/O port states.
* *
@ -251,7 +221,7 @@ typedef struct {
* *
* @notapi * @notapi
*/ */
#define pal_lld_readport(port) PAL_SIUL_READ_PORT(port) #define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
/** /**
* @brief Reads the output latch. * @brief Reads the output latch.
@ -263,7 +233,7 @@ typedef struct {
* *
* @notapi * @notapi
*/ */
#define pal_lld_readlatch(port) PAL_SIUL_READ_LATCH(port) #define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
/** /**
* @brief Writes a bits mask on a I/O port. * @brief Writes a bits mask on a I/O port.
@ -273,7 +243,37 @@ typedef struct {
* *
* @notapi * @notapi
*/ */
#define pal_lld_writeport(port, bits) PAL_SIUL_WRITE_PORT(port, bits) #define pal_lld_writeport(port, bits) \
(((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
/**
* @brief Reads a group of bits.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @return The group logical states.
*
* @notapi
*/
#define pal_lld_readgroup(port, mask, offset) \
_pal_lld_readgroup(port, mask, offset)
/**
* @brief Writes a group of bits.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group width
* are masked.
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) \
_pal_lld_writegroup(port, mask, offset, bits)
#endif /* SPC5_SIU_SUPPORTS_PORTS */
/** /**
* @brief Pads group mode setup. * @brief Pads group mode setup.
@ -370,6 +370,13 @@ extern const PALConfig pal_default_config;
extern "C" { extern "C" {
#endif #endif
void _pal_lld_init(const PALConfig *config); void _pal_lld_init(const PALConfig *config);
ioportmask_t _pal_lld_readgroup(ioportid_t port,
ioportmask_t mask,
uint_fast8_t offset);
void _pal_lld_writegroup(ioportid_t port,
ioportmask_t mask,
uint_fast8_t offset,
ioportmask_t bits);
void _pal_lld_setgroupmode(ioportid_t port, void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask, ioportmask_t mask,
iomode_t mode); iomode_t mode);