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ChibiOS
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It compiles, not tested and unfinished. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11179 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-12-24 18:42:36 +00:00
parent 17fa448323
commit 6f646de79b
3 changed files with 194 additions and 53 deletions
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8
demos/STM32/RT-STM32H743I-NUCLEO144/main.c
View File

@ -29,9 +29,9 @@ static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("blinker");
while (true) {
palSetLine(LINE_ARD_D13);
// palSetLine(LINE_ARD_D13);
chThdSleepMilliseconds(500);
palClearLine(LINE_ARD_D13);
// palClearLine(LINE_ARD_D13);
chThdSleepMilliseconds(500);
}
}
@ -54,8 +54,8 @@ int main(void) {
/*
* ARD_D13 is programmed as output (board LED).
*/
palClearLine(LINE_ARD_D13);
palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
// palClearLine(LINE_ARD_D13);
// palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
/*
* Activates the serial driver 1 using the driver default configuration.

25
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -104,7 +104,7 @@ static inline void init_pwr(void) {
#if STM32_PWR_CR2 & PWR_CR2_BREN
while ((PWR->CR2 & PWR_CR2_BRRDY) == 0)
;
rccEnableBKPSRAM(false);
rccEnableBKPRAM(false);
#endif
#if STM32_PWR_CR3 & PWR_CR3_USB33DEN
while ((PWR->CR3 & PWR_CR3_USB33RDY) == 0)
@ -134,23 +134,20 @@ void hal_lld_init(void) {
rccResetAHB1(~0);
rccResetAHB2(~0);
rccResetAHB3(~(RCC_AHB3RSTR_CPURST | RCC_AHB3RSTR_FMCRST));
rccResetAHB4(~STM32_GPIO_EN_MASK);
rccResetAHB4(~(STM32_GPIO_EN_MASK));
rccResetAPB1L(~0);
rccResetAPB1H(~0);
rccResetAPB2(~0);
rccResetAPB3(~0);
rccResetAPB4(~0);
/* Backup domain initialization.*/
init_bkp_domain();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* IRQ subsystem initialization.*/
irqInit();
// irqInit();
}
/**
@ -166,6 +163,9 @@ void stm32_clock_init(void) {
/* PWR initialization.*/
init_pwr();
/* Backup domain initialization.*/
init_bkp_domain();
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
@ -180,10 +180,11 @@ void stm32_clock_init(void) {
; /* Wait until HSI is selected. */
/* Registers cleared to reset values.*/
RCC->CR = RCC_CR_HSION; /* CR Reset value. */
RCC->ICSCR = 0x40000000; /* ICSCR Reset value. */
RCC->CFGR = 0x00000000; /* CFGR reset value. */
RCC->CSR = 0x00000000; /* CSR reset value. */
RCC->CR = RCC_CR_HSION; /* CR Reset value. */
RCC->ICSCR = 0x40000000; /* ICSCR Reset value. */
RCC->CFGR = 0x00000000; /* CFGR reset value. */
RCC->CSR = 0x00000000; /* CSR reset value. */
RCC->PLLCFGR = 0x01FF0000; /* PLLCFGR reset value. */
/* HSE activation with optional bypass.*/
#if STM32_HSE_ENABLED == TRUE
@ -274,7 +275,7 @@ void stm32_clock_init(void) {
while ((RCC->CR & rdymask) != rdymask)
;
}
#endif
#endif /* STM32_PLL1_ENABLED || STM32_PLL2_ENABLED || STM32_PLL3_ENABLED */
/* Other clock-related settings.*/
RCC->CFGR = STM32_MCO2SEL | RCC_CFGR_MCO2PRE_VALUE(STM32_MCO2PRE_VALUE) |
@ -305,7 +306,7 @@ void stm32_clock_init(void) {
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB4(RCC_APB4ENR_SYSCFGEN);
rccEnableAPB4(RCC_APB4ENR_SYSCFGEN, true);
}
/** @} */

214
os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
View File

@ -53,41 +53,77 @@
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
* @param[in] mask APB1 peripherals mask, low set
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1(mask, lp) { \
RCC->APB1ENR |= (mask); \
#define rccEnableAPB1L(mask, lp) { \
RCC->APB1LENR |= (mask); \
if (lp) \
RCC->APB1LPENR |= (mask); \
RCC->APB1LLPENR |= (mask); \
}
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask, high set
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1H(mask, lp) { \
RCC->APB1HENR |= (mask); \
if (lp) \
RCC->APB1HLPENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
* @param[in] mask APB1 peripherals mask, low set
*
* @api
*/
#define rccDisableAPB1(mask, lp) { \
RCC->APB1ENR &= ~(mask); \
if (lp) \
RCC->APB1LPENR &= ~(mask); \
#define rccDisableAPB1L(mask) { \
RCC->APB1LENR &= ~(mask); \
RCC->APB1LLPENR &= ~(mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask, high set
*
* @api
*/
#define rccDisableAPB1H(mask) { \
RCC->APB1HENR &= ~(mask); \
RCC->APB1HLPENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
* @param[in] mask APB1 peripherals mask, low set
*
* @api
*/
#define rccResetAPB1(mask) { \
RCC->APB1RSTR |= (mask); \
RCC->APB1RSTR = 0; \
#define rccResetAPB1L(mask) { \
RCC->APB1LRSTR |= (mask); \
RCC->APB1LRSTR = 0; \
}
/**
* @brief Resets one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask, high set
*
* @api
*/
#define rccResetAPB1H(mask) { \
RCC->APB1HRSTR |= (mask); \
RCC->APB1HRSTR = 0; \
}
/**
@ -108,14 +144,12 @@
* @brief Disables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB2(mask, lp) { \
#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
if (lp) \
RCC->APB2LPENR &= ~(mask); \
RCC->APB2LPENR &= ~(mask); \
}
/**
@ -130,6 +164,82 @@
RCC->APB2RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB3(mask, lp) { \
RCC->APB3ENR |= (mask); \
if (lp) \
RCC->APB3LPENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
*
* @api
*/
#define rccDisableAPB3(mask) { \
RCC->APB3ENR &= ~(mask); \
RCC->APB3LPENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB3 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccResetAPB3(mask) { \
RCC->APB3RSTR |= (mask); \
RCC->APB3RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB4 bus.
*
* @param[in] mask APB4 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB4(mask, lp) { \
RCC->APB4ENR |= (mask); \
if (lp) \
RCC->APB4LPENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB4 bus.
*
* @param[in] mask APB4 peripherals mask
*
* @api
*/
#define rccDisableAPB4(mask) { \
RCC->APB4ENR &= ~(mask); \
RCC->APB4LPENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB4 bus.
*
* @param[in] mask APB4 peripherals mask
*
* @api
*/
#define rccResetAPB4(mask) { \
RCC->APB4RSTR |= (mask); \
RCC->APB4RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB1 bus.
*
@ -148,14 +258,12 @@
* @brief Disables the clock of one or more peripheral on the AHB1 bus.
*
* @param[in] mask AHB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAHB1(mask, lp) { \
#define rccDisableAHB1(mask) { \
RCC->AHB1ENR &= ~(mask); \
if (lp) \
RCC->AHB1LPENR &= ~(mask); \
RCC->AHB1LPENR &= ~(mask); \
}
/**
@ -188,14 +296,12 @@
* @brief Disables the clock of one or more peripheral on the AHB2 bus.
*
* @param[in] mask AHB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAHB2(mask, lp) { \
#define rccDisableAHB2(mask) { \
RCC->AHB2ENR &= ~(mask); \
if (lp) \
RCC->AHB2LPENR &= ~(mask); \
RCC->AHB2LPENR &= ~(mask); \
}
/**
@ -211,7 +317,7 @@
}
/**
* @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
* @brief Enables the clock of one or more peripheral on the AHB3 bus.
*
* @param[in] mask AHB3 peripherals mask
* @param[in] lp low power enable flag
@ -225,21 +331,19 @@
}
/**
* @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
* @brief Disables the clock of one or more peripheral on the AHB3 bus.
*
* @param[in] mask AHB3 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAHB3(mask, lp) { \
#define rccDisableAHB3(mask) { \
RCC->AHB3ENR &= ~(mask); \
if (lp) \
RCC->AHB3LPENR &= ~(mask); \
RCC->AHB3LPENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
* @brief Resets one or more peripheral on the AHB3 bus.
*
* @param[in] mask AHB3 peripherals mask
*
@ -249,6 +353,44 @@
RCC->AHB3RSTR |= (mask); \
RCC->AHB3RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB4 bus.
*
* @param[in] mask AHB4 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB4(mask, lp) { \
RCC->AHB4ENR |= (mask); \
if (lp) \
RCC->AHB4LPENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB4 bus.
*
* @param[in] mask AHB4 peripherals mask
*
* @api
*/
#define rccDisableAHB4(mask) { \
RCC->AHB4ENR &= ~(mask); \
RCC->AHB4LPENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the AHB4 bus.
*
* @param[in] mask AHB4 peripherals mask
*
* @api
*/
#define rccResetAHB4(mask) { \
RCC->AHB4RSTR |= (mask); \
RCC->AHB4RSTR = 0; \
}
/** @} */
/**
@ -427,16 +569,14 @@
*
* @api
*/
#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
#define rccEnableBKPRAM(lp) rccEnableAHB4(RCC_AHB4ENR_BKPRAMEN, lp)
/**
* @brief Disables the BKPSRAM peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
#define rccDisableBKPSRAM() rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN)
/** @} */
/**