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QUADSPI settings in all registries and platform.mk. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9535 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2016-05-26 12:57:35 +00:00
parent d22d4c839e
commit 6f7ae6af72
10 changed files with 136 additions and 0 deletions
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24
os/hal/ports/STM32/STM32F0xx/stm32_registry.h
View File

@ -153,6 +153,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -412,6 +415,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -613,6 +619,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -822,6 +831,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1046,6 +1058,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1274,6 +1289,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1530,6 +1548,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1802,6 +1823,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

18
os/hal/ports/STM32/STM32F1xx/stm32_registry.h
View File

@ -138,6 +138,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -336,6 +339,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -512,6 +518,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -718,6 +727,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -964,6 +976,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1212,6 +1227,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

6
os/hal/ports/STM32/STM32F37x/stm32_registry.h
View File

@ -134,6 +134,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -382,6 +385,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

36
os/hal/ports/STM32/STM32F3xx/stm32_registry.h
View File

@ -164,6 +164,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -428,6 +431,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -672,6 +678,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -885,6 +894,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1095,6 +1107,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1322,6 +1337,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1568,6 +1586,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1798,6 +1819,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -2012,6 +2036,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -2238,6 +2265,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -2469,6 +2499,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -2710,6 +2743,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

5
os/hal/ports/STM32/STM32F4xx/platform.mk
View File

@ -31,6 +31,9 @@ endif
ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
endif
ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
endif
ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c
endif
@ -74,6 +77,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c \
@ -99,6 +103,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1 \

29
os/hal/ports/STM32/STM32F4xx/stm32_registry.h
View File

@ -217,6 +217,13 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
#define STM32_QUADSPI1_HANDLER Vector1AC
#define STM32_QUADSPI1_NUMBER 91
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -571,6 +578,13 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
#define STM32_QUADSPI1_HANDLER Vector1AC
#define STM32_QUADSPI1_NUMBER 91
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -906,6 +920,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1268,6 +1285,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#if !defined(STM32F2XX)
@ -1584,6 +1604,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -1865,6 +1888,9 @@
STM32_DMA_STREAM_ID_MSK(1, 1))
#define STM32_I2C4_TX_DMA_CHN 0x00040020
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@ -2123,6 +2149,9 @@
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

5
os/hal/ports/STM32/STM32F7xx/platform.mk
View File

@ -31,6 +31,9 @@ endif
ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
endif
ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
endif
ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c
endif
@ -74,6 +77,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c \
@ -99,6 +103,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2 \

7
os/hal/ports/STM32/STM32F7xx/stm32_registry.h
View File

@ -215,6 +215,13 @@
#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
#define STM32_I2C4_TX_DMA_CHN 0x00200000
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
#define STM32_QUADSPI1_HANDLER Vector1B0
#define STM32_QUADSPI1_NUMBER 92
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

3
os/hal/ports/STM32/STM32L0xx/stm32_registry.h
View File

@ -141,6 +141,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE

3
os/hal/ports/STM32/STM32L1xx/stm32_registry.h
View File

@ -184,6 +184,9 @@
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#if (STM32L1XX_PROD_CAT == 1) || defined(__DOXYGEN__)