From 6fcfdc6686ccb794b390007aa98d2a3f2ef033bf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Jul 2010 06:20:12 +0000 Subject: [PATCH] Fixed bugs 3025133, 3025549, 3025854, 3026528, 3027975. Implemented CR 3023944. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.0.x@2063 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/Doxyfile | 2 +- os/hal/platforms/STM32/hal_lld_f103.h | 78 ++++++++++++++++++++++ os/hal/platforms/STM32/hal_lld_f105_f107.h | 75 ++++++++++++++++++++- os/hal/platforms/STM32/spi_lld.c | 8 +-- os/kernel/include/ch.h | 4 +- os/kernel/src/chheap.c | 6 +- os/ports/GCC/ARMCMx/STM32F10x/vectors.s | 7 ++ os/ports/GCC/ARMCMx/chcore.h | 25 +++++-- os/ports/GCC/MSP430/chcore.c | 2 +- readme.txt | 11 +++ 10 files changed, 201 insertions(+), 17 deletions(-) diff --git a/docs/Doxyfile b/docs/Doxyfile index 8ec001333..d0b0779b9 100644 --- a/docs/Doxyfile +++ b/docs/Doxyfile @@ -31,7 +31,7 @@ PROJECT_NAME = ChibiOS/RT # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 2.0.1 +PROJECT_NUMBER = 2.0.2 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/os/hal/platforms/STM32/hal_lld_f103.h b/os/hal/platforms/STM32/hal_lld_f103.h index 17d797a84..2f234aa83 100644 --- a/os/hal/platforms/STM32/hal_lld_f103.h +++ b/os/hal/platforms/STM32/hal_lld_f103.h @@ -86,6 +86,84 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ +#define USB_HP_CAN1_TX_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ +#define USB_LP_CAN1_RX0_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#endif +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#endif +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#endif +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#if defined(STM32F10X_MD) || defined(STM32F10X_HD) || defined(__DOXYGEN__) +#define USART3_IRQHandler VectorDC /**< USART3. */ +#endif +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USBWakeUp_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#if defined(STM32F10X_HD) || defined(__DOXYGEN__) +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define ADC3_IRQHandler VectorFC /**< ADC3. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define SDIO_IRQHandler Vector104 /**< SDIO. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ +#endif + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/hal_lld_f105_f107.h b/os/hal/platforms/STM32/hal_lld_f105_f107.h index ddd664e7e..5f03dbe2c 100644 --- a/os/hal/platforms/STM32/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32/hal_lld_f105_f107.h @@ -95,6 +95,77 @@ #define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ #define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTCAlarm_IRQHandler VectorE4 /**< RTC alarm through EXTI + line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ +#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ +#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ +#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */ +#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -167,7 +238,7 @@ #endif /** - * @brief PLL2 multiplier value. + * @brief PLL2 multiplier value. * @note The default value is calculated for a 72MHz system clock from * a 25MHz crystal using both PLL and PLL2. */ @@ -264,7 +335,7 @@ for the PLL clock */ #if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__) /** - * @brief PLL2 input frequency. + * @brief PLL2 input frequency. */ #define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 6774beec6..7fa719a7a 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -94,14 +94,14 @@ static void spi_start_wait(SPIDriver *spip, size_t n, spip->spd_dmatx->CNDTR = (uint32_t)n; spip->spd_dmatx->CCR |= ccr; - /* DMAs start.*/ - spip->spd_dmarx->CCR |= DMA_CCR1_EN; - spip->spd_dmatx->CCR |= DMA_CCR1_EN; - /* SPI enable.*/ chSysLock(); spip->spd_spi->CR1 |= SPI_CR1_SPE; + /* DMAs start.*/ + spip->spd_dmarx->CCR |= DMA_CCR1_EN; + spip->spd_dmatx->CCR |= DMA_CCR1_EN; + /* Wait for completion event.*/ spip->spd_thread = currp; chSchGoSleepS(THD_STATE_SUSPENDED); diff --git a/os/kernel/include/ch.h b/os/kernel/include/ch.h index 281aa7183..26adf1a66 100644 --- a/os/kernel/include/ch.h +++ b/os/kernel/include/ch.h @@ -46,7 +46,7 @@ /** * @brief Kernel version string. */ -#define CH_KERNEL_VERSION "2.0.1" +#define CH_KERNEL_VERSION "2.0.2" /** * @brief Kernel version major number. @@ -61,7 +61,7 @@ /** * @brief Kernel version patch number. */ -#define CH_KERNEL_PATCH 1 +#define CH_KERNEL_PATCH 2 /* * Common values. diff --git a/os/kernel/src/chheap.c b/os/kernel/src/chheap.c index b22b43bac..8a7b8a1cf 100644 --- a/os/kernel/src/chheap.c +++ b/os/kernel/src/chheap.c @@ -48,6 +48,8 @@ #if CH_USE_HEAP +#if !CH_USE_MALLOC_HEAP + /* * Defaults on the best synchronization mechanism available. */ @@ -59,8 +61,6 @@ #define H_UNLOCK(h) chSemSignal(&(h)->h_sem) #endif -#if !CH_USE_MALLOC_HEAP - /** * @brief Default heap descriptor. */ @@ -260,7 +260,7 @@ size_t chHeapStatus(MemoryHeap *heapp, size_t *sizep) { #if CH_USE_MUTEXES #define H_LOCK() chMtxLock(&hmtx) -#define H_UNLOCK() chMtxUnock() +#define H_UNLOCK() chMtxUnlock() static Mutex hmtx; #elif CH_USE_SEMAPHORES #define H_LOCK() chSemWait(&hsem) diff --git a/os/ports/GCC/ARMCMx/STM32F10x/vectors.s b/os/ports/GCC/ARMCMx/STM32F10x/vectors.s index db7d0fab9..68e16812a 100644 --- a/os/ports/GCC/ARMCMx/STM32F10x/vectors.s +++ b/os/ports/GCC/ARMCMx/STM32F10x/vectors.s @@ -27,6 +27,13 @@ .syntax unified .thumb +/* If the macro is not defined in the Makefile then a board.h file must be + provided containing the definition of the STM32 family member.*/ +#if !defined(STM32F10X_LD) && !defined(STM32F10X_MD) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_CL) +#include "board.h" +#endif + .section vectors _vectors: .word __ram_end__ diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index cda270aee..04bc6ad47 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -135,7 +135,7 @@ * to user in the ARMv6-M port. */ #ifndef CORTEX_PRIORITY_SVCALL -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) #else /* If it is externally redefined then better perform a validity check on it.*/ #if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) @@ -153,7 +153,7 @@ * the minimum priority level. */ #ifndef CORTEX_PRIORITY_PENDSV -#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY +#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY #else /* If it is externally redefined then better perform a validity check on it.*/ #if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV) @@ -171,6 +171,17 @@ #define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) #endif +/** + * @brief Stack alignment enforcement. + * @note The default value is 64 in order to comply with EABI, reducing + * the value to 32 can save some RAM space if you don't care about + * binary compatibility with EABI compiled libraries. + * @note Allowed values are 32 or 64. + */ +#ifndef CORTEX_STACK_ALIGNMENT +#define CORTEX_STACK_ALIGNMENT 64 +#endif + /*===========================================================================*/ /* Port exported info. */ /*===========================================================================*/ @@ -218,9 +229,15 @@ /*===========================================================================*/ /** - * @brief 32 bits stack and memory alignment enforcement. + * @brief Stack and memory alignment enforcement. */ -typedef uint32_t stkalign_t; +#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__) +typedef uint64_t stkalign_t __attribute__ ((aligned (8))); +#elif CORTEX_STACK_ALIGNMENT == 32 +typedef uint32_t stkalign_t __attribute__ ((aligned (4))); +#else +#error "invalid stack alignment selected" +#endif /** * @brief Generic ARM register. diff --git a/os/ports/GCC/MSP430/chcore.c b/os/ports/GCC/MSP430/chcore.c index 56e779560..8b6075a61 100644 --- a/os/ports/GCC/MSP430/chcore.c +++ b/os/ports/GCC/MSP430/chcore.c @@ -58,7 +58,7 @@ void port_switch(Thread *ntp, Thread *otp) { "push r8 \n\t" \ "push r7 \n\t" \ "push r6 \n\t" \ - "push r6 \n\t" \ + "push r5 \n\t" \ "push r4"); otp->p_ctx.sp = sp; sp = ntp->p_ctx.sp; diff --git a/readme.txt b/readme.txt index 772ffde3a..e5e5bf5b9 100644 --- a/readme.txt +++ b/readme.txt @@ -58,6 +58,17 @@ *** Releases *** ***************************************************************************** +*** 2.0.2 *** +- FIX: Fixed invalid contex restore in MSP430 port (bug 3027975). +- FIX: Fixed STM32 vectors file (bug 3026528). +- FIX: Fixed race condition in STM32 SPI driver (bug 3025854). +- FIX: Fixed H_LOCK and H_UNLOCK redefined with CH_USE_MALLOC_HEAP (bug + 3025549). +- FIX: Added option to enforce the stack alignment to 32 or 64 bits in the + Cortex-Mx port (bug 3025133). +- NEW: Added friendly interrupt vectors names to the STM32 HAL (change request + 3023944). + *** 2.0.1 *** - FIX: Fixed notification order in input queues (bug 3020708). - FIX: Fixed non functional CH_CURRP_REGISTER_CACHE option in the Cortex-M3