From 70574490da58814907c28067a494697f37b1d615 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 5 Aug 2014 14:37:04 +0000 Subject: [PATCH] STM32 FSMC NAND. Cleaned rest of v2.6 calls git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7130 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/emc_lld.c | 14 ++--- os/hal/ports/STM32/LLD/emcnand_lld.c | 26 ++++----- testhal/STM32/STM32F4xx/FSMC_NAND/.cproject | 65 +++++++++++++++++++++ testhal/STM32/STM32F4xx/FSMC_NAND/.project | 44 ++++++++++++++ testhal/STM32/STM32F4xx/FSMC_NAND/main.c | 23 ++++---- 5 files changed, 138 insertions(+), 34 deletions(-) create mode 100644 testhal/STM32/STM32F4xx/FSMC_NAND/.cproject create mode 100644 testhal/STM32/STM32F4xx/FSMC_NAND/.project diff --git a/os/hal/ports/STM32/LLD/emc_lld.c b/os/hal/ports/STM32/LLD/emc_lld.c index 2706fd8c3..885a12965 100644 --- a/os/hal/ports/STM32/LLD/emc_lld.c +++ b/os/hal/ports/STM32/LLD/emc_lld.c @@ -106,8 +106,7 @@ void emc_lld_start(EMCDriver *emcp) { rccResetFSMC(); rccEnableFSMC(FALSE); #if STM32_EMC_USE_INT - nvicEnableVector(FSMC_IRQn, - CORTEX_PRIORITY_MASK(STM32_EMC_FSMC1_IRQ_PRIORITY)); + nvicEnableVector(FSMC_IRQn, STM32_EMC_FSMC1_IRQ_PRIORITY); #endif /* STM32_EMC_USE_INT */ } #endif /* PLATFORM_STM32_USE_EMC1 */ @@ -150,9 +149,8 @@ void emc_lld_stop(EMCDriver *emcp) { * @notapi */ void emc_lld_serve_interrupt(void) { -#warning "This functionality untested" - chDbgPanic("Unrealized"); + osalSysHalt("Unrealized"); } /** @@ -161,17 +159,19 @@ void emc_lld_serve_interrupt(void) { * @notapi */ CH_IRQ_HANDLER(FSMC_IRQHandler) { -#warning "This functionality untested" + osalSysHalt("This functionality untested"); CH_IRQ_PROLOGUE(); - +#if STM32_EMCNAND_USE_EMCNAND1 if (EMCD1.nand1->SR & FSMC_SR_ISR_MASK){ EMCNANDD1.isr_handler(&EMCNANDD1, EMCD1.nand1->SR); } +#endif +#if STM32_EMCNAND_USE_EMCNAND2 if (EMCD1.nand2->SR & FSMC_SR_ISR_MASK){ EMCNANDD2.isr_handler(&EMCNANDD2, EMCD1.nand2->SR); } - +#endif CH_IRQ_EPILOGUE(); } #endif /* STM32_EMC_USE_INT */ diff --git a/os/hal/ports/STM32/LLD/emcnand_lld.c b/os/hal/ports/STM32/LLD/emcnand_lld.c index a00ae7121..9ed6db9bd 100644 --- a/os/hal/ports/STM32/LLD/emcnand_lld.c +++ b/os/hal/ports/STM32/LLD/emcnand_lld.c @@ -74,16 +74,10 @@ EMCNANDDriver EMCNANDD2; * * @notapi */ -static void wakeup_isr(EMCNANDDriver *emcnandp, msg_t msg){ +static void wakeup_isr(EMCNANDDriver *emcnandp){ osalDbgCheck(emcnandp->thread != NULL); - - if (emcnandp->thread) { - thread_t *tp = emcnandp->thread; - emcnandp->thread = NULL; - tp->p_u.rdymsg = msg; - chSchReadyI(tp); - } + osalThreadResumeI(&emcnandp->thread, MSG_OK); } /** @@ -93,8 +87,8 @@ static void wakeup_isr(EMCNANDDriver *emcnandp, msg_t msg){ */ static void emcnand_lld_suspend_thread(EMCNANDDriver *emcnandp) { - emcnandp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); + //emcnandp->thread = chThdGetSelfX(); + osalThreadSuspendS(&emcnandp->thread); } /** @@ -130,7 +124,7 @@ static uint32_t calc_eccps(EMCNANDDriver *emcnandp){ */ static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) { emcnandp->nand->SR |= FSMC_SR_IREN; - chDbgPanic("Function untested"); + osalSysHalt("Function untested"); } /** @@ -142,7 +136,7 @@ static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) { */ static void emcnand_ready_isr_disable(EMCNANDDriver *emcnandp) { emcnandp->nand->SR &= ~FSMC_SR_IREN; - chDbgPanic("Function untested"); + osalSysHalt("Function untested"); } /** @@ -158,7 +152,7 @@ static void emcnand_isr_handler (EMCNANDDriver *emcnandp, (void)emcnandp; (void)flags; - chDbgPanic("Unrealized"); + osalSysHalt("Unrealized"); } #else /* STM32_EMC_USE_INT */ /** @@ -205,13 +199,13 @@ static void emcnand_isr_handler(EMCNANDDriver *emcnandp){ case EMCNAND_ERASE: /* NAND reports about erase finish */ emcnandp->state = EMCNAND_READY; - wakeup_isr(emcnandp, MSG_OK); + wakeup_isr(emcnandp); break; case EMCNAND_PROGRAM: /* NAND reports about page programming finish */ emcnandp->state = EMCNAND_READY; - wakeup_isr(emcnandp, MSG_OK); + wakeup_isr(emcnandp); break; default: @@ -257,7 +251,7 @@ static void emcnand_lld_serve_transfer_end_irq(EMCNANDDriver *emcnandp, emcnandp->state = EMCNAND_READY; emcnandp->rxdata = NULL; emcnandp->datalen = 0; - wakeup_isr(emcnandp, MSG_OK); + wakeup_isr(emcnandp); break; default: diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject b/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject new file mode 100644 index 000000000..a89cdbc06 --- /dev/null +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/.project b/testhal/STM32/STM32F4xx/FSMC_NAND/.project new file mode 100644 index 000000000..8fb3b9c90 --- /dev/null +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/.project @@ -0,0 +1,44 @@ + + + STM32F4xx-FSMC_NAND + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + + + CHIBIOS + file:/home/barthess/projects/chibios-svn + + + diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c index 3811986d3..ac9f571b5 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c @@ -51,6 +51,8 @@ ****************************************************************************** */ +#define USE_KILL_BLOCK_TEST FALSE + #define EMCNAND_TIME_SET ((uint32_t) 2) //(8nS) #define EMCNAND_TIME_WAIT ((uint32_t) 6) //(30nS) #define EMCNAND_TIME_HOLD ((uint32_t) 1) //(5nS) @@ -69,8 +71,6 @@ #define NAND_STATUS_READY ((uint8_t)1 << 6) #define NAND_STATUS_NOT_RPOTECTED ((uint8_t)1 << 7) -#define EMCNAND_USE_KILL_TEST TRUE - /* ****************************************************************************** * EXTERNS @@ -82,9 +82,11 @@ * PROTOTYPES ****************************************************************************** */ +#if !STM32_EMC_EMCNAND_USE_FSMC_INT static void ready_isr_enable(void); static void ready_isr_disable(void); static void nand_ready_cb(EXTDriver *extp, expchannel_t channel); +#endif /* ****************************************************************************** @@ -141,6 +143,7 @@ static const EMCNANDConfig nandcfg = { /** * */ +#if !STM32_EMC_EMCNAND_USE_FSMC_INT static const EXTConfig extcfg = { { {EXT_CH_MODE_DISABLED, NULL}, //0 @@ -168,6 +171,7 @@ static const EXTConfig extcfg = { {EXT_CH_MODE_DISABLED, NULL}, } }; +#endif /* !STM32_EMC_EMCNAND_USE_FSMC_INT */ /* * @@ -175,7 +179,7 @@ static const EXTConfig extcfg = { volatile uint32_t IdleCnt = 0; volatile systime_t T = 0; -#if EMCNAND_USE_KILL_TEST +#if USE_KILL_BLOCK_TEST volatile uint32_t KillCycle = 0; #endif @@ -187,12 +191,12 @@ volatile uint32_t KillCycle = 0; ****************************************************************************** */ +#if !STM32_EMC_EMCNAND_USE_FSMC_INT static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){ (void)extp; (void)channel; -#if !STM32_EMC_EMCNAND_USE_FSMC_INT + EMCNANDD1.isr_handler(&EMCNANDD1); -#endif } static void ready_isr_enable(void) { @@ -202,6 +206,7 @@ static void ready_isr_enable(void) { static void ready_isr_disable(void) { extChannelDisable(&EXTD1, GPIOD_NAND_RB); } +#endif static void nand_wp_assert(void) { palClearPad(GPIOB, GPIOB_NAND_WP); @@ -562,7 +567,9 @@ int main(void) { chSysInit(); emcStart(&EMCD1, &emccfg); +#if !STM32_EMC_EMCNAND_USE_FSMC_INT extStart(&EXTD1, &extcfg); +#endif emcnandStart(&EMCNANDD1, &nandcfg); chThdSleepMilliseconds(4000); @@ -616,12 +623,6 @@ int main(void) { while (TRUE) { chThdSleepMilliseconds(500); } - - /*warning suppressor */ -#if STM32_EMC_EMCNAND_USE_FSMC_INT - (void)ready_isr_enable; - (void)ready_isr_disable; -#endif }