Mirrored SPIR as SPI3.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14506 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -127,7 +127,7 @@
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*/
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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@ -144,8 +144,8 @@
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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/*
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* GPT driver system settings.
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@ -161,10 +161,10 @@
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#define STM32_I2C_USE_I2C1 TRUE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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@ -211,10 +211,13 @@
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*/
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#define STM32_SPI_USE_SPI1 TRUE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_SPI_USE_SPI3 TRUE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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@ -238,12 +241,12 @@
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 TRUE
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#define STM32_UART_USE_LPUART1 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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@ -234,7 +234,11 @@ void spi_lld_init(void) {
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#if STM32_SPI_USE_SPI3
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spiObjectInit(&SPID3);
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#if !defined(SUBGHZSPI)
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SPID3.spi = SPI3;
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#else
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SPID3.spi = SUBGHZSPI;
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#endif
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SPID3.dmarx = NULL;
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SPID3.dmatx = NULL;
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SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_STREAM) |
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@ -73,8 +73,8 @@
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#define STM32_DMAMUX1_TIM17_UP 38
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#define STM32_DMAMUX1_AES_IN 39
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#define STM32_DMAMUX1_AES_OUT 40
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#define STM32_DMAMUX1_SGSPI_RX 41
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#define STM32_DMAMUX1_SGSPI_TX 42
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#define STM32_DMAMUX1_SPI3_RX 41
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#define STM32_DMAMUX1_SPI3_TX 42
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/** @} */
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/*===========================================================================*/
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@ -646,21 +646,21 @@
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*
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* @api
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*/
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#define rccEnableSPIR(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp)
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#define rccEnableSPI3(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp)
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/**
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* @brief Disables the SPIR peripheral clock.
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*
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* @api
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*/
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#define rccDisableSPIR() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN)
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#define rccDisableSPI3() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN)
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/**
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* @brief Resets the SPIR peripheral.
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*
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* @api
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*/
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#define rccResetSPIR() rccResetAPB3(RCC_APB3RSTR_SUBGHZSPIRST)
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#define rccResetSPI3() rccResetAPB3(RCC_APB3RSTR_SUBGHZSPIRST)
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/** @} */
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/**
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@ -234,7 +234,9 @@
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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