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ChibiOS
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Mirrored SPIR as SPI3. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14506 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-06-06 17:55:52 +00:00
parent 3b7148ad70
commit 713e9fcc6c
5 changed files with 32 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h
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@ -127,7 +127,7 @@
*/ */
#define STM32_ADC_COMPACT_SAMPLES FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -144,8 +144,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/* /*
* GPT driver system settings. * GPT driver system settings.
@ -161,10 +161,10 @@
#define STM32_I2C_USE_I2C1 TRUE #define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C1_DMA_PRIORITY 3
@ -211,10 +211,13 @@
*/ */
#define STM32_SPI_USE_SPI1 TRUE #define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
@ -238,12 +241,12 @@
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_LPUART1 FALSE #define STM32_UART_USE_LPUART1 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/* /*

4
os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c
View File

@ -234,7 +234,11 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI3 #if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3); spiObjectInit(&SPID3);
#if !defined(SUBGHZSPI)
SPID3.spi = SPI3; SPID3.spi = SPI3;
#else
SPID3.spi = SUBGHZSPI;
#endif
SPID3.dmarx = NULL; SPID3.dmarx = NULL;
SPID3.dmatx = NULL; SPID3.dmatx = NULL;
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_STREAM) | SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_STREAM) |

4
os/hal/ports/STM32/STM32WLxx/stm32_dmamux.h
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@ -73,8 +73,8 @@
#define STM32_DMAMUX1_TIM17_UP 38 #define STM32_DMAMUX1_TIM17_UP 38
#define STM32_DMAMUX1_AES_IN 39 #define STM32_DMAMUX1_AES_IN 39
#define STM32_DMAMUX1_AES_OUT 40 #define STM32_DMAMUX1_AES_OUT 40
#define STM32_DMAMUX1_SGSPI_RX 41 #define STM32_DMAMUX1_SPI3_RX 41
#define STM32_DMAMUX1_SGSPI_TX 42 #define STM32_DMAMUX1_SPI3_TX 42
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/

6
os/hal/ports/STM32/STM32WLxx/stm32_rcc.h
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@ -646,21 +646,21 @@
* *
* @api * @api
*/ */
#define rccEnableSPIR(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp) #define rccEnableSPI3(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp)
/** /**
* @brief Disables the SPIR peripheral clock. * @brief Disables the SPIR peripheral clock.
* *
* @api * @api
*/ */
#define rccDisableSPIR() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN) #define rccDisableSPI3() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN)
/** /**
* @brief Resets the SPIR peripheral. * @brief Resets the SPIR peripheral.
* *
* @api * @api
*/ */
#define rccResetSPIR() rccResetAPB3(RCC_APB3RSTR_SUBGHZSPIRST) #define rccResetSPI3() rccResetAPB3(RCC_APB3RSTR_SUBGHZSPIRST)
/** @} */ /** @} */
/** /**

4
os/hal/ports/STM32/STM32WLxx/stm32_registry.h
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@ -234,7 +234,9 @@
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI4 FALSE
#define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI5 FALSE
#define STM32_HAS_SPI6 FALSE #define STM32_HAS_SPI6 FALSE