Support for STM32H750B-DK:
- Added STM32H750xB.ld - Added ST_STM32H750XB_DISCOVERY board - Updated hal_mii.h - Added RT-STM32H750XB-DISCOVERY demo git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13890 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* ST32F750xB generic setup.
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*
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* AXI SRAM - BSS, Data, Heap.
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* SRAM1+SRAM2 - None.
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* SRAM3 - NOCACHE, ETH.
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* SRAM4 - None.
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* DTCM-RAM - Main Stack, Process Stack.
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* ITCM-RAM - None.
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* BCKP SRAM - None.
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*/
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MEMORY
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{
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flash0 : org = 0x08000000, len = 128k /* Flash bank 1 */
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flash1 : org = 0x00000000, len = 0
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flash2 : org = 0x00000000, len = 0
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flash3 : org = 0x00000000, len = 0
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flash4 : org = 0x00000000, len = 0
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flash5 : org = 0x00000000, len = 0
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flash6 : org = 0x00000000, len = 0
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flash7 : org = 0x00000000, len = 0
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ram0 : org = 0x24000000, len = 512k /* AXI SRAM */
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ram1 : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
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ram2 : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
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ram3 : org = 0x30040000, len = 32k /* AHB SRAM3 */
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ram4 : org = 0x38000000, len = 64k /* AHB SRAM4 */
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ram5 : org = 0x20000000, len = 128k /* DTCM-RAM */
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ram6 : org = 0x00000000, len = 64k /* ITCM-RAM */
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ram7 : org = 0x38800000, len = 4k /* BCKP SRAM */
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}
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/* For each data/text section two region are defined, a virtual region
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and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash0);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash0);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash0);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash0);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram5);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram5);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Stack rules inclusion.*/
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INCLUDE rules_stacks.ld
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/*===========================================================================*/
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/* Custom sections for STM32H7xx. */
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/* SRAM3 is assumed to be marked non-cacheable using MPU. */
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/*===========================================================================*/
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/* RAM region to be used for nocache segment.*/
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REGION_ALIAS("NOCACHE_RAM", ram3);
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/* RAM region to be used for eth segment.*/
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REGION_ALIAS("ETH_RAM", ram3);
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SECTIONS
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{
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/* Special section for non cache-able areas.*/
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.nocache (NOLOAD) : ALIGN(4)
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{
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__nocache_base__ = .;
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*(.nocache)
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*(.nocache.*)
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*(.bss.__nocache_*)
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. = ALIGN(4);
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__nocache_end__ = .;
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} > NOCACHE_RAM
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/* Special section for Ethernet DMA non cache-able areas.*/
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.eth (NOLOAD) : ALIGN(4)
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{
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__eth_base__ = .;
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*(.eth)
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*(.eth.*)
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*(.bss.__eth_*)
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. = ALIGN(4);
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__eth_end__ = .;
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} > ETH_RAM
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}
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/* Code rules inclusion.*/
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INCLUDE rules_code.ld
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/* Data rules inclusion.*/
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INCLUDE rules_data.ld
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/* Memory rules inclusion.*/
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INCLUDE rules_memory.ld
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@ -169,6 +169,7 @@
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#define MII_LAN8710A_ID 0x0007C0F1
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#define MII_LAN8710A_ID 0x0007C0F1
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#define MII_LAN8720_ID 0x0007C0F0
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#define MII_LAN8720_ID 0x0007C0F0
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#define MII_LAN8742A_ID 0x0007C130
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#define MII_LAN8742A_ID 0x0007C130
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#define MII_LAN8740A_ID 0x0007C110
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/** @} */
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/** @} */
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#endif /* MII_H */
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#endif /* MII_H */
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