From 7431f3a069d1c79d11556a079c6427f5710bf6b1 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 31 Jan 2020 08:38:57 +0000 Subject: [PATCH] Made H7 HAL core-aware. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13316 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../RT-STM32H755I-NUCLEO144/cfg/mcuconf.h | 1 - os/hal/ports/STM32/STM32H7xx/hal_lld.c | 9 +++- os/hal/ports/STM32/STM32H7xx/hal_lld.h | 47 ++++++++++++++----- os/hal/ports/STM32/STM32H7xx/stm32_registry.h | 10 ++++ .../conf/mcuconf_stm32h743xx/mcuconf.h.ftl | 9 +++- 5 files changed, 59 insertions(+), 17 deletions(-) diff --git a/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h index de36f80ca..c8d3eb032 100644 --- a/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h @@ -44,7 +44,6 @@ * General settings. */ #define STM32_NO_INIT FALSE -#define STM32_SYS_CK_ENFORCED_VALUE STM32_HSICLK /* * Memory attributes settings. diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c index 8ea0d7d50..28fed93d3 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -135,6 +135,7 @@ static inline void init_pwr(void) { */ void hal_lld_init(void) { +#if STM32_NO_INIT == FALSE /* Reset of all peripherals. AHB3 is not reset entirely because FMC could have been initialized in the board initialization file (board.c). Note, GPIOs are not reset because initialized before this point in @@ -149,6 +150,7 @@ void hal_lld_init(void) { rccResetAPB2(~0); rccResetAPB3(~0); rccResetAPB4(~0); +#endif /* STM32_NO_INIT == FALSE */ /* DMA subsystems initialization.*/ #if defined(STM32_BDMA_REQUIRED) @@ -157,6 +159,9 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif +#if defined(STM32_MDMA_REQUIRED) + mdmaInit(); +#endif /* IRQ subsystem initialization.*/ irqInit(); @@ -204,6 +209,7 @@ void hal_lld_init(void) { * @special */ void stm32_clock_init(void) { +#if STM32_NO_INIT == FALSE uint32_t cfgr; #if 0 @@ -211,7 +217,6 @@ void stm32_clock_init(void) { (void)rcc; #endif -#if STM32_NO_INIT == FALSE #if defined(STM32_ENFORCE_H7_REV_V) /* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data read corruption. @@ -407,12 +412,12 @@ void stm32_clock_init(void) { STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL | STM32_USART1SEL; #endif -#endif /* STM32_NO_INIT */ /* RAM1 2 and 3 clocks enabled.*/ rccEnableSRAM1(true); rccEnableSRAM2(true); rccEnableSRAM3(true); +#endif /* STM32_NO_INIT */ } /** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 15c31cf93..9c679bf40 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -586,16 +586,19 @@ */ /** * @brief Disables the PWR/RCC initialization in the HAL. + * @note All the clock tree constants are calculated but the initialization + * is not performed. */ #if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) #define STM32_NO_INIT FALSE #endif /** - * @brief SYS_CK value assumed if @p STM32_NO_INIT is enabled. + * @brief Target code for this HAL configuration. + * @note Core 1 is the Cortex-M7, core 2 is the Cortex-M4. */ -#if !defined(STM32_SYS_CK_ENFORCED_VALUE) || defined(__DOXYGEN__) -#define STM32_SYS_CK_ENFORCED_VALUE STM32_HSICLK +#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__) +#define STM32_TARGET_CORE 1 #endif /** @@ -2071,10 +2074,7 @@ /** * @brief System clock source. */ -#if STM32_NO_INIT || defined(__DOXYGEN__) -#define STM32_SYS_CK STM32_SYS_CK_ENFORCED_VALUE - -#elif (STM32_SW == STM32_SW_HSI_CK) +#if (STM32_SW == STM32_SW_HSI_CK) || defined(__DOXYGEN__) #define STM32_SYS_CK STM32_HSI_CK #elif (STM32_SW == STM32_SW_CSI_CK) @@ -2232,11 +2232,6 @@ #error "invalid STM32_D1CPRE value specified" #endif -/** - * @brief Core clock. - */ -#define STM32_CORE_CK STM32_SYS_D1CPRE_CK - /** * @brief HCLK clock. */ @@ -2262,6 +2257,34 @@ #error "invalid STM32_D1HPRE value specified" #endif +/** + * @brief Core clock. + */ +#define STM32_CORE1_CK STM32_SYS_D1CPRE_CK + +/** + * @brief Core clock. + */ +#define STM32_CORE2_CK STM32_HCLK + +#if (STM32_TARGET_CORE == 1) || defined(__DOXYGEN__) + +#if STM32_HAS_M7 != TRUE +#error "Cortex-M7 not present in this device" +#endif +#define STM32_CORE_CK STM32_CORE1_CK + +#elif STM32_TARGET_CORE == 2 + +#if STM32_HAS_M4 != TRUE +#error "Cortex-M4 not present in this device" +#endif +#define STM32_CORE_CK STM32_CORE2_CK + +#else +#error "invalid STM32_TARGET_CORE value specified" +#endif + /* * AHB frequency check. */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h index 6cb6c3d4f..02b283d40 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -32,6 +32,16 @@ /* RNG attributes.*/ #define STM32_HAS_RNG1 TRUE +/* Cores.*/ +#if defined(STM32H750xx) || defined(STM32H742xx) || \ + defined(STM32H743xx) || defined(STM32H753xx) +#define STM32_HAS_M7 TRUE +#define STM32_HAS_M4 FALSE +#else +#define STM32_HAS_M7 TRUE +#define STM32_HAS_M4 TRUE +#endif + /** * @name STM32H7xx capabilities * @{ diff --git a/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl index bd9f1c492..dea2fc43e 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl @@ -46,12 +46,16 @@ #define STM32H742_MCUCONF #define STM32H743_MCUCONF #define STM32H753_MCUCONF +#define STM32H745_MCUCONF +#define STM32H755_MCUCONF +#define STM32H747_MCUCONF +#define STM32H757_MCUCONF /* * General settings. */ #define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"} -#define STM32_SYS_CK_ENFORCED_VALUE ${doc.STM32_SYS_CK_ENFORCED_VALUE!"STM32_HSICLK"} +#define STM32_TARGET_CORE ${doc.STM32_NO_INIT!"1"} /* * Memory attributes settings. @@ -61,7 +65,8 @@ /* * PWR system settings. - * Reading STM32 Reference Manual is required. + * Reading STM32 Reference Manual is required, settings in PWR_CR3 are + * very critical. * Register constants are taken from the ST header. */ #define STM32_ODEN ${doc.STM32_ODEN!"STM32_ODEN_DISABLED"}