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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14603 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2021-07-16 04:22:42 +00:00
parent 98ccc315fa
commit 7474921bb2
3 changed files with 16 additions and 1 deletions
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2
os/hal/ports/STM32/STM32G0xx/hal_lld.c
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@ -643,7 +643,7 @@ void stm32_clock_init(void) {
rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false); rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false);
#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN) #if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, false); rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, true);
#endif #endif
/* Static PWR configurations.*/ /* Static PWR configurations.*/

10
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -780,6 +780,11 @@ void stm32_clock_init(void) {
among multiple drivers.*/ among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false); rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
/* RTC APB clock enable.*/
#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true)
#endif
/* Static PWR configurations.*/ /* Static PWR configurations.*/
hal_lld_set_static_pwr(); hal_lld_set_static_pwr();
@ -839,6 +844,11 @@ void stm32_clock_init(void) {
among multiple drivers.*/ among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false); rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
/* RTC APB clock enable.*/
#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true)
#endif
/* Static PWR configurations.*/ /* Static PWR configurations.*/
hal_lld_set_static_pwr(); hal_lld_set_static_pwr();

5
os/hal/ports/STM32/STM32L4xx/hal_lld.c
View File

@ -106,6 +106,11 @@ void stm32_clock_init(void) {
/* PWR clock enabled.*/ /* PWR clock enabled.*/
rccEnablePWRInterface(false); rccEnablePWRInterface(false);
/* RTC APB clock enable.*/
#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true)
#endif
/* Core voltage setup, backup domain access enabled and left open.*/ /* Core voltage setup, backup domain access enabled and left open.*/
PWR->CR1 = STM32_VOS | PWR_CR1_DBP; PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */ while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */