diff --git a/demos/STM32/RT-STM32H563ZI-NUCLEO144/main.c b/demos/STM32/RT-STM32H563ZI-NUCLEO144/main.c index 77be31e6c..34fe0d453 100644 --- a/demos/STM32/RT-STM32H563ZI-NUCLEO144/main.c +++ b/demos/STM32/RT-STM32H563ZI-NUCLEO144/main.c @@ -95,12 +95,12 @@ static void cmd_clock(BaseSequentialStream *chp, int argc, char *argv[]) { return; } + /* Time for the serial TX buffer to flush.*/ + chThdSleepMilliseconds(100); + /* Switching clocks.*/ result = halClockSwitchMode(ccp); - /* Time for allowing serial buffers to be flushed.*/ - chThdSleepMilliseconds(10); - /* Reconfiguring the peripherals because clocks frequencies could have changed.*/ sioStart(&SIOD3, NULL); diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c index 994a61355..12d1868d8 100644 --- a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c @@ -209,9 +209,70 @@ __STATIC_INLINE void usart_init(SIODriver *siop) { USART_TypeDef *u = siop->usart; uint32_t presc, brr, clock; + /*Clock input frequency, it could be dynamic.*/ + if (false) { + } +#if STM32_SIO_USE_USART1 == TRUE + else if (&SIOD1 == siop) { + clock = STM32_USART1CLK; + } +#endif +#if STM32_SIO_USE_USART2 == TRUE + else if (&SIOD2 == siop) { + clock = STM32_USART2CLK; + } +#endif +#if STM32_SIO_USE_USART3 == TRUE + else if (&SIOD3 == siop) { + clock = STM32_USART3CLK; + } +#endif +#if STM32_SIO_USE_UART4 == TRUE + else if (&SIOD4 == siop) { + clock = STM32_UART4CLK; + } +#endif +#if STM32_SIO_USE_UART5 == TRUE + else if (&SIOD5 == siop) { + clock = STM32_UART5CLK; + } +#endif +#if STM32_SIO_USE_USART6 == TRUE + else if (&SIOD6 == siop) { + clock = STM32_USART6CLK; + } +#endif +#if STM32_SIO_USE_UART7 == TRUE + else if (&SIOD7 == siop) { + clock = STM32_UART7CLK; + } +#endif +#if STM32_SIO_USE_UART8 == TRUE + else if (&SIOD8 == siop) { + clock = STM32_UART8CLK; + } +#endif +#if STM32_SIO_USE_UART9 == TRUE + else if (&SIOD9 == siop) { + clock = STM32_UART9CLK; + } +#endif +#if STM32_SIO_USE_USART10 == TRUE + else if (&SIOD10 == siop) { + clock = STM32_USART10CLK; + } +#endif +#if STM32_SIO_USE_LPUART1 == TRUE + else if (&LPSIOD1 == siop) { + clock = STM32_LPUART1CLK; + } +#endif + else { + osalDbgAssert(false, "invalid SIO instance"); + } + /* Prescaler calculation.*/ static const uint32_t prescvals[] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; - clock = siop->clock; presc = prescvals[siop->config->presc]; /* Baud rate setting.*/ @@ -271,57 +332,46 @@ void sio_lld_init(void) { #if STM32_SIO_USE_USART1 == TRUE sioObjectInit(&SIOD1); SIOD1.usart = USART1; - SIOD1.clock = STM32_USART1CLK; #endif #if STM32_SIO_USE_USART2 == TRUE sioObjectInit(&SIOD2); SIOD2.usart = USART2; - SIOD2.clock = STM32_USART2CLK; #endif #if STM32_SIO_USE_USART3 == TRUE sioObjectInit(&SIOD3); SIOD3.usart = USART3; - SIOD3.clock = STM32_USART3CLK; #endif #if STM32_SIO_USE_UART4 == TRUE sioObjectInit(&SIOD4); SIOD4.usart = UART4; - SIOD4.clock = STM32_UART4CLK; #endif #if STM32_SIO_USE_UART5 == TRUE sioObjectInit(&SIOD5); SIOD5.usart = UART5; - SIOD5.clock = STM32_UART5CLK; #endif #if STM32_SIO_USE_USART6 == TRUE sioObjectInit(&SIOD6); SIOD6.usart = USART6; - SIOD6.clock = STM32_USART6CLK; #endif #if STM32_SIO_USE_UART7 == TRUE sioObjectInit(&SIOD7); SIOD7.usart = UART7; - SIOD7.clock = STM32_UART7CLK; #endif #if STM32_SIO_USE_UART8 == TRUE sioObjectInit(&SIOD8); SIOD8.usart = UART8; - SIOD8.clock = STM32_UART8CLK; #endif #if STM32_SIO_USE_UART9 == TRUE sioObjectInit(&SIOD9); SIOD9.usart = UART9; - SIOD9.clock = STM32_UART9CLK; #endif #if STM32_SIO_USE_USART10 == TRUE sioObjectInit(&SIOD10); SIOD10.usart = USART10; - SIOD10.clock = STM32_USART10CLK; #endif #if STM32_SIO_USE_LPUART1 == TRUE sioObjectInit(&LPSIOD1); LPSIOD1.usart = LPUART1; - LPSIOD1.clock = STM32_LPUART1CLK; #endif } @@ -343,7 +393,7 @@ msg_t sio_lld_start(SIODriver *siop) { if (siop->state == SIO_STOP) { - /* Enables the peripheral.*/ + /* Enables the peripheral.*/ if (false) { } #if STM32_SIO_USE_USART1 == TRUE diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h index 57a4e7a13..ddc77ceb4 100644 --- a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h @@ -333,9 +333,7 @@ */ #define sio_lld_driver_fields \ /* Pointer to the USARTx registers block.*/ \ - USART_TypeDef *usart; \ - /* Clock frequency for the associated USART/UART.*/ \ - uint32_t clock + USART_TypeDef *usart /** * @brief Low level fields of the SIO configuration structure. diff --git a/os/hal/ports/STM32/STM32H5xx/hal_lld.c b/os/hal/ports/STM32/STM32H5xx/hal_lld.c index 2ad712174..1154074f5 100644 --- a/os/hal/ports/STM32/STM32H5xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H5xx/hal_lld.c @@ -31,7 +31,7 @@ /** * @brief Number of thresholds in the wait states array. */ -#define STM32_WS_THRESHOLDS 5 +#define STM32_WS_THRESHOLDS 6 /** * @name Registers reset values @@ -209,7 +209,7 @@ static const system_limits_t vos_range0 = { .sysclk_max = STM32_VOS0_SYSCLK_MAX, .flash_thresholds = {STM32_VOS0_0WS_THRESHOLD, STM32_VOS0_1WS_THRESHOLD, STM32_VOS0_2WS_THRESHOLD, STM32_VOS0_3WS_THRESHOLD, - STM32_VOS0_4WS_THRESHOLD} + STM32_VOS0_4WS_THRESHOLD, STM32_VOS0_5WS_THRESHOLD} }; /** @@ -219,7 +219,7 @@ static const system_limits_t vos_range1 = { .sysclk_max = STM32_VOS1_SYSCLK_MAX, .flash_thresholds = {STM32_VOS1_0WS_THRESHOLD, STM32_VOS1_1WS_THRESHOLD, STM32_VOS1_2WS_THRESHOLD, STM32_VOS1_3WS_THRESHOLD, - STM32_VOS1_4WS_THRESHOLD} + STM32_VOS1_4WS_THRESHOLD, STM32_VOS0_5WS_THRESHOLD} }; /** @@ -229,7 +229,7 @@ static const system_limits_t vos_range2 = { .sysclk_max = STM32_VOS2_SYSCLK_MAX, .flash_thresholds = {STM32_VOS2_0WS_THRESHOLD, STM32_VOS2_1WS_THRESHOLD, STM32_VOS2_2WS_THRESHOLD, STM32_VOS2_3WS_THRESHOLD, - STM32_VOS2_4WS_THRESHOLD} + STM32_VOS2_4WS_THRESHOLD, STM32_VOS0_5WS_THRESHOLD} }; /** @@ -239,7 +239,7 @@ static const system_limits_t vos_range3 = { .sysclk_max = STM32_VOS3_SYSCLK_MAX, .flash_thresholds = {STM32_VOS3_0WS_THRESHOLD, STM32_VOS3_1WS_THRESHOLD, STM32_VOS3_2WS_THRESHOLD, STM32_VOS3_3WS_THRESHOLD, - STM32_VOS3_4WS_THRESHOLD} + STM32_VOS3_4WS_THRESHOLD, STM32_VOS0_5WS_THRESHOLD} }; #endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */ diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_limits.h b/os/hal/ports/STM32/STM32H5xx/stm32_limits.h index a52ff5e13..3484627e8 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_limits.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_limits.h @@ -54,6 +54,7 @@ #define STM32_VOS0_2WS_THRESHOLD 126000000 #define STM32_VOS0_3WS_THRESHOLD 168000000 #define STM32_VOS0_4WS_THRESHOLD 210000000 +#define STM32_VOS0_5WS_THRESHOLD 250000000 /** @} */ /** @@ -85,6 +86,7 @@ #define STM32_VOS1_2WS_THRESHOLD 102000000 #define STM32_VOS1_3WS_THRESHOLD 136000000 #define STM32_VOS1_4WS_THRESHOLD 170000000 +#define STM32_VOS1_5WS_THRESHOLD 200000000 /** @} */ /** @@ -115,7 +117,8 @@ #define STM32_VOS2_1WS_THRESHOLD 60000000 #define STM32_VOS2_2WS_THRESHOLD 90000000 #define STM32_VOS2_3WS_THRESHOLD 120000000 -#define STM32_VOS2_4WS_THRESHOLD 0 +#define STM32_VOS2_4WS_THRESHOLD 150000000 +#define STM32_VOS2_5WS_THRESHOLD 150000000 /** @} */ /** @@ -146,7 +149,8 @@ #define STM32_VOS3_1WS_THRESHOLD 40000000 #define STM32_VOS3_2WS_THRESHOLD 60000000 #define STM32_VOS3_3WS_THRESHOLD 80000000 -#define STM32_VOS3_4WS_THRESHOLD 0 +#define STM32_VOS3_4WS_THRESHOLD 100000000 +#define STM32_VOS3_5WS_THRESHOLD 100000000 /** @} */ /**