diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
index 730ff7615..54cbc8091 100644
--- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
+++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
@@ -441,10 +441,11 @@ void dac_lld_start(DACDriver *dacp) {
       /* Operating in SINGLE mode with one channel to set. Set registers for
          specified channel from configuration. Lower half word of
          configuration specifies configuration for any channel.*/
+#if STM32_DAC_HAS_MCR == TRUE
       reg = dacp->params->dac->MCR & dacp->params->regmask;
       dacp->params->dac->MCR = reg |
         ((dacp->config->mcr & ~dacp->params->regmask) << dacp->params->regshift);
-
+#endif
       /* Enable and initialise the channel.*/
       reg = dacp->params->dac->CR;
       reg &= dacp->params->regmask;
@@ -457,8 +458,9 @@ void dac_lld_start(DACDriver *dacp) {
        both channels from configuration. Lower and upper half words specify
        configuration for channels CH1 & CH2 respectively.*/
     (void)channel;
+#if STM32_DAC_HAS_MCR == TRUE
     dacp->params->dac->MCR = dacp->config->mcr;
-
+#endif
     /* Enable and initialise both CH1 and CH2. Mask out DMA and calibrate.*/
     reg = dacp->config->cr;
     reg &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2 | DAC_CR_CEN1 | DAC_CR_CEN2);
@@ -810,15 +812,19 @@ void dac_lld_stop_conversion(DACDriver *dacp) {
   /* Restore start configuration but leave DORx at current values.*/
   cr = dacp->params->dac->CR;
 #if STM32_DAC_DUAL_MODE == FALSE
+#if STM32_DAC_HAS_MCR == TRUE
   uint32_t mcr;
   mcr = dacp->params->dac->MCR & dacp->params->regmask;
   dacp->params->dac->MCR = mcr |
     ((dacp->config->mcr & dacp->params->regmask) << dacp->params->regshift);
+#endif
   cr &= dacp->params->regmask;
   cr |= (DAC_CR_EN1 | (dacp->config->cr & ~dacp->params->regmask)) <<
                                       dacp->params->regshift;
 #else
+#if STM32_DAC_HAS_MCR == TRUE
   dacp->params->dac->MCR = dacp->config->mcr;
+#endif
   cr = dacp->config->cr | DAC_CR_EN1 | DAC_CR_EN2;
 #endif
 
diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
index 7fefd5327..2d1358989 100644
--- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
+++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
@@ -39,6 +39,14 @@
  * @name    Configuration options
  * @{
  */
+
+/**
+ * @brief   DAC mode control register.
+ */
+#if !defined(STM32_DAC_HAS_MCR) || defined(__DOXYGEN__)
+#define STM32_DAC_HAS_MCR                   FALSE
+#endif
+
 /**
  * @brief   Enables the DAC dual mode.
  * @note    In dual mode DAC second channels cannot be accessed individually.
@@ -574,9 +582,11 @@ typedef enum {
 
 /**
  * @brief   Low level fields of the DAC configuration structure.
- * @note    In DUAL mode init, cr and mcr fields hold CH1 settings in their
- *          lower 16 bits and CH2 settings in the upper 16 bits.
+ * @note    In DUAL mode init, cr and mcr (if available) fields hold CH1
+ *          settings in their lower 16 bits and CH2 settings in the upper
+ *          16 bits.
  */
+#if STM32_DAC_HAS_MCR == TRUE
 #define dac_lld_config_fields                                               \
   /* Initial output on DAC channel.*/                                       \
   uint32_t                init;                                             \
@@ -586,6 +596,14 @@ typedef enum {
   uint32_t                cr;                                               \
   /* DAC mode control register.*/                                           \
   uint32_t                mcr
+#else
+#define dac_lld_config_fields                                               \
+  /* Initial output on DAC channel.*/                                       \
+  uint32_t                init;                                             \
+  /* DAC data holding register mode.*/                                      \
+  dacdhrmode_t            datamode;                                         \
+  /* DAC control register.*/                                                \
+  uint32_t                cr
 
 /**
  * @brief   Low level fields of the DAC group configuration structure.
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
index 2ef5d9765..5ea333702 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
@@ -62,6 +62,9 @@
 /* Common.                                                                   */
 /*===========================================================================*/
 
+/* DAC attributes.*/
+#define STM32_DAC_HAS_MCR                   TRUE
+
 /* RNG attributes.*/
 #define STM32_HAS_RNG1                      TRUE
 
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
index ba8a1d686..ae45e8b15 100644
--- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
@@ -38,6 +38,9 @@
 /* Common.                                                                   */
 /*===========================================================================*/
 
+/* DAC attributes.*/
+#define STM32_DAC_HAS_MCR                   TRUE
+
 /* RNG attributes.*/
 #define STM32_HAS_RNG1                      TRUE