G4-related fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13015 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
cc1aadc935
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764ff2ab16
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32G4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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#define STM32G473_MCUCONF
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#define STM32G483_MCUCONF
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#define STM32G474_MCUCONF
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#define STM32G484_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PWR_CR2 (STM32_PLS_LEV0 | \
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STM32_PVDE_DISABLED)
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#define STM32_HSI16_ENABLED FALSE
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#define STM32_HSI48_ENABLED FALSE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLLRCLK
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#define STM32_PLLSRC STM32_PLLSRC_HSI16
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#define STM32_PLLM_VALUE 4
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#define STM32_PLLN_VALUE 84
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#define STM32_PLLP_VALUE 7
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#define STM32_PLLQ_VALUE 8
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#define STM32_PLLR_VALUE 2
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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/*
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* Peripherals clock sources.
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*/
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
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#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
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#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
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#define STM32_I2C2SEL STM32_I2C2SEL_PCLK
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
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#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
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#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
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#define STM32_FDCANSEL STM32_FDCANSEL_HSE
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#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
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#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
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#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
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#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
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#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_40_41_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_22_29_PRIORITY 6
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#define STM32_IRQ_EXTI30_31_32_PRIORITY 6
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#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_TIM8_BRK_PRIORITY 7
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#define STM32_IRQ_TIM8_UP_PRIORITY 7
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#define STM32_IRQ_TIM8_TRGCO_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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#define STM32_IRQ_TIM20_BRK_PRIORITY 7
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#define STM32_IRQ_TIM20_UP_PRIORITY 7
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#define STM32_IRQ_TIM20_TRGCO_PRIORITY 7
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#define STM32_IRQ_TIM20_CC_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 3
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#define STM32_IRQ_USART2_PRIORITY 3
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#define STM32_IRQ_USART3_PRIORITY 3
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#define STM32_IRQ_UART4_PRIORITY 3
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#define STM32_IRQ_UART5_PRIORITY 3
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#define STM32_IRQ_LPUART1_PRIORITY 3
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/*
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* ADC driver system settings.
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*/
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/*
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* CAN driver system settings.
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*/
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/*
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* DAC driver system settings.
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*/
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/*
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* GPT driver system settings.
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*/
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/*
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* I2C driver system settings.
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*/
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/*
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* ICU driver system settings.
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*/
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/*
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* PWM driver system settings.
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*/
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/*
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* RTC driver system settings.
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*/
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/*
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* SDC driver system settings.
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*/
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/*
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* SERIAL driver system settings.
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*/
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/*
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* SPI driver system settings.
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*/
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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/*
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* TRNG driver system settings.
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*/
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/*
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* UART driver system settings.
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*/
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/*
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* USB driver system settings.
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*/
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/*
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* WDG driver system settings.
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*/
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/*
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* WSPI driver system settings.
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*/
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#endif /* MCUCONF_H */
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@ -281,10 +281,10 @@
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#define STM32_ADC12SEL_PLLPCLK (1U << 30U) /**< ADC12 source is PLLPCLK. */
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#define STM32_ADC12SEL_SYSCLK (2U << 30U) /**< ADC12 source is SYSCLK. */
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#define STM32_ADC34SEL_MASK (3U << 30U) /**< ADC34SEL mask. */
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#define STM32_ADC34SEL_NOCLK (0U << 30U) /**< ADC34 source is none. */
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#define STM32_ADC34SEL_PLLPCLK (1U << 30U) /**< ADC34 source is PLLPCLK. */
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#define STM32_ADC34SEL_SYSCLK (2U << 30U) /**< ADC34 source is SYSCLK. */
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#define STM32_ADC345SEL_MASK (3U << 30U) /**< ADC345SEL mask. */
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#define STM32_ADC345SEL_NOCLK (0U << 30U) /**< ADC345 source is none. */
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#define STM32_ADC345SEL_PLLPCLK (1U << 30U) /**< ADC345 source is PLLPCLK. */
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#define STM32_ADC345SEL_SYSCLK (2U << 30U) /**< ADC345 source is SYSCLK. */
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/** @} */
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/**
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@ -415,7 +415,7 @@
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLM_VALUE 2
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#define STM32_PLLM_VALUE 4
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#endif
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/**
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@ -425,7 +425,7 @@
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLN_VALUE 16
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#define STM32_PLLN_VALUE 84
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#endif
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/**
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@ -433,7 +433,7 @@
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* @note The allowed values are 7, 17.
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*/
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#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLP_VALUE 7
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#endif
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/**
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@ -441,7 +441,7 @@
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* @note The allowed values are 2, 4, 6, 8.
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*/
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#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLQ_VALUE 4
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#define STM32_PLLQ_VALUE 8
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#endif
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/**
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/**
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* @brief ADC34 clock source.
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*/
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#if !defined(STM32_ADC34SEL) || defined(__DOXYGEN__)
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#define STM32_ADC34SEL STM32_ADC34SEL_PLLPCLK
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#if !defined(STM32_ADC345SEL) || defined(__DOXYGEN__)
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#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
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#endif
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/**
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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* - STM32G431xx, STM32G441xx, STM32G471xx.
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* - STM32G473xx, STM32G483xx.
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* - STM32G474xx, STM32G484xx.
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* - STM32GBK1CB.
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/*
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* Configuration-related checks.
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#if (STM32_SW == STM32_SW_PLLRCLK) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
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(STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
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(STM32_ADC12SEL == STM32_ADC34SEL_PLLPCLK) || \
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(STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
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(STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
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(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
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* @brief STM32_PLLPEN field.
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*/
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#if (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
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(STM32_ADC34SEL == STM32_ADC34SEL_PLLPCLK) || \
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(STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
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defined(__DOXYGEN__)
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#define STM32_PLLPEN (1 << 16)
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#else
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@ -1671,13 +1667,13 @@
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* @brief ADC clock frequency.
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*/
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#if (STM32_ADC12SEL == STM32_ADC12SEL_NOCLK) || defined(__DOXYGEN__)
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#define STM32_ADCCLK 0
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#define STM32_ADC12CLK 0
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#elif STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK
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#define STM32_ADCCLK STM32_PLL_P_CLKOUT
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#define STM32_ADC12CLK STM32_PLL_P_CLKOUT
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#elif STM32_ADC12SEL == STM32_ADC12SEL_HSI16
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#define STM32_ADCCLK STM32_HSI16CLK
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#define STM32_ADC12CLK STM32_HSI16CLK
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#else
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#error "invalid source selected for ADC clock"
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@ -1686,14 +1682,14 @@
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/**
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* @brief ADC clock frequency.
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*/
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#if (STM32_ADC34SEL == STM32_ADC34SEL_NOCLK) || defined(__DOXYGEN__)
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#define STM32_ADCCLK 0
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#if (STM32_ADC345SEL == STM32_ADC345SEL_NOCLK) || defined(__DOXYGEN__)
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#define STM32_ADC345CLK 0
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#elif STM32_ADC34SEL == STM32_ADC34SEL_PLLPCLK
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#define STM32_ADCCLK STM32_PLL_P_CLKOUT
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#elif STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK
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#define STM32_ADC345CLK STM32_PLL_P_CLKOUT
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#elif STM32_ADC34SEL == STM32_ADC34SEL_HSI16
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#define STM32_ADCCLK STM32_HSI16CLK
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#elif STM32_ADC345SEL == STM32_ADC345SEL_HSI16
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#define STM32_ADC345CLK STM32_HSI16CLK
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#else
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#error "invalid source selected for ADC clock"
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