[KINETIS] ADC LLD files.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7250 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -41,6 +41,9 @@
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#define KINETIS_PORTD_IRQ_VECTOR VectorEC
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#define KINETIS_PORTD_IRQ_VECTOR VectorEC
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#define KINETIS_PORTE_IRQ_VECTOR VectorF0
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#define KINETIS_PORTE_IRQ_VECTOR VectorF0
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/* ADC attributes.*/
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#define KINETIS_HAS_ADC0 TRUE
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#define KINETIS_ADC0_IRC_VECTOR Vector98
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/** @} */
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/** @} */
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@ -6,6 +6,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
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${CHIBIOS}/os/hal/ports/KINETIS/K20x/spi_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/K20x/spi_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/ext_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/ext_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/adc_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/K20x/gpt_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/K20x/gpt_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/K20x/st_lld.c
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${CHIBIOS}/os/hal/ports/KINETIS/K20x/st_lld.c
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@ -38,6 +38,10 @@
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#define KINETIS_PORTA_IRQ_VECTOR VectorB8
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#define KINETIS_PORTA_IRQ_VECTOR VectorB8
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#define KINETIS_PORTD_IRQ_VECTOR VectorBC
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#define KINETIS_PORTD_IRQ_VECTOR VectorBC
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/* ADC attributes.*/
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#define KINETIS_HAS_ADC0 TRUE
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#define KINETIS_ADC0_IRC_VECTOR Vector7C
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/** @} */
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/** @} */
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#endif /* _KINETIS_REGISTRY_H_ */
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#endif /* _KINETIS_REGISTRY_H_ */
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@ -5,6 +5,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
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${CHIBIOS}/os/hal/ports/KINETIS/KL2x/serial_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/KL2x/serial_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/ext_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/ext_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/LLD/adc_lld.c \
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${CHIBIOS}/os/hal/ports/KINETIS/KL2x/st_lld.c
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${CHIBIOS}/os/hal/ports/KINETIS/KL2x/st_lld.c
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# Required include directories
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# Required include directories
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@ -0,0 +1,258 @@
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/*
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ChibiOS/HAL - Copyright (C) 2014 Derek Mulcahy
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file KINETIS/LLD/adc_lld.c
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* @brief KINETIS ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define ADC_CHANNEL_MASK 0x1f
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void calibrate(ADCDriver *adcp) {
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/* Clock Divide by 8, Use Bus Clock Div 2 */
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/* At 48MHz this results in ADCCLK of 48/8/2 == 3MHz */
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adcp->adc->CFG1 = ADCx_CFG1_ADIV(ADCx_CFG1_ADIV_DIV_8) |
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ADCx_CFG1_ADICLK(ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2);
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/* Use software trigger and disable DMA etc. */
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adcp->adc->SC2 = 0;
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/* Enable Hardware Average, Average 32 Samples, Calibrate */
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adcp->adc->SC3 = ADCx_SC3_AVGE |
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ADCx_SC3_AVGS(ADCx_SC3_AVGS_AVERAGE_32_SAMPLES) |
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ADCx_SC3_CAL;
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/* FIXME: May take several ms. Use an interrupt instead of busy wait */
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/* Wait for calibration completion */
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while (!(adcp->adc->SC1A & ADCx_SC1n_COCO))
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;
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uint16_t gain = ((adcp->adc->CLP0 + adcp->adc->CLP1 + adcp->adc->CLP2 +
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adcp->adc->CLP3 + adcp->adc->CLP4 + adcp->adc->CLPS) / 2) | 0x8000;
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adcp->adc->PG = gain;
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gain = ((adcp->adc->CLM0 + adcp->adc->CLM1 + adcp->adc->CLM2 +
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adcp->adc->CLM3 + adcp->adc->CLM4 + adcp->adc->CLMS) / 2) | 0x8000;
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adcp->adc->MG = gain;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(KINETIS_ADC0_IRC_VECTOR) {
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OSAL_IRQ_PROLOGUE();
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ADCDriver *adcp = &ADCD1;
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/* Disable Interrupt, Disable Channel */
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adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
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/* Read the sample into the buffer */
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adcp->samples[adcp->current_index++] = adcp->adc->RA;
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bool more = true;
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/* At the end of the buffer then we may be finished */
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if (adcp->current_index == adcp->number_of_samples) {
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_adc_isr_full_code(&ADCD1);
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adcp->current_index = 0;
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/* We are never finished in circular mode */
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more = ADCD1.grpp->circular;
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}
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if (more) {
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/* Signal half completion in circular mode. */
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if (ADCD1.grpp->circular &&
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(adcp->current_index == (adcp->number_of_samples / 2))) {
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_adc_isr_half_code(&ADCD1);
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}
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/* Skip to the next channel */
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do {
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adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
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} while (((1 << adcp->current_channel) & adcp->grpp->channel_mask) == 0);
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/* Enable Interrupt, Select the Channel */
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adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
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}
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if KINETIS_ADC_USE_ADC0
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled.*/
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nvicEnableVector(ADC0_IRQn, KINETIS_ADC_IRQ_PRIORITY);
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC clock.*/
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if (adcp->state == ADC_STOP) {
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SIM->SCGC6 |= SIM_SCGC6_ADC0;
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#if KINETIS_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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adcp->adc = ADC0;
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if (adcp->config->calibrate) {
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calibrate(adcp);
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}
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}
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#endif /* KINETIS_ADC_USE_ADC0 */
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock.*/
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if (adcp->state == ADC_READY) {
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SIM->SCGC6 &= ~SIM_SCGC6_ADC0;
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#if KINETIS_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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/* Disable Interrupt, Disable Channel */
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adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
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}
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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const ADCConversionGroup *grpp = adcp->grpp;
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/* Enable the Bandgap Buffer if channel mask includes BANDGAP */
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if (grpp->channel_mask & ADC_BANDGAP) {
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PMC->REGSC |= PMC_REGSC_BGBE;
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}
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adcp->number_of_samples = adcp->depth * grpp->num_channels;
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adcp->current_index = 0;
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/* Skip to the next channel */
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adcp->current_channel = 0;
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while (((1 << adcp->current_channel) & grpp->channel_mask) == 0) {
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adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
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}
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/* Set clock speed and conversion size */
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adcp->adc->CFG1 = grpp->cfg1;
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/* Set averaging */
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adcp->adc->SC3 = grpp->sc3;
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/* Enable Interrupt, Select Channel */
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adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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const ADCConversionGroup *grpp = adcp->grpp;
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/* Disable the Bandgap buffer if channel mask includes BANDGAP */
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if (grpp->channel_mask & ADC_BANDGAP) {
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/* Clear BGBE, ACKISO is w1c, avoid setting */
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PMC->REGSC &= ~(PMC_REGSC_BGBE | PMC_REGSC_ACKISO);
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}
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}
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#endif /* HAL_USE_ADC */
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/** @} */
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@ -0,0 +1,360 @@
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/*
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ChibiOS/HAL - Copyright (C) 2014 Derek Mulcahy
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file KINETIS/LLD/adc_lld.h
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* @brief KINETIS ADC subsystem low level driver header.
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*
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* @addtogroup ADC
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* @{
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*/
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#ifndef _ADC_LLD_H_
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#define _ADC_LLD_H_
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Minimum ADC clock frequency.
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*/
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#define KINETIS_ADCCLK_MIN 600000
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/**
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* @brief Maximum ADC clock frequency.
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*/
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#define KINETIS_ADCCLK_MAX 36000000
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#define ADCx_SC3_AVGS_AVERAGE_4_SAMPLES 0
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#define ADCx_SC3_AVGS_AVERAGE_8_SAMPLES 1
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#define ADCx_SC3_AVGS_AVERAGE_16_SAMPLES 2
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#define ADCx_SC3_AVGS_AVERAGE_32_SAMPLES 3
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#define ADCx_CFG1_ADIV_DIV_1 0
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#define ADCx_CFG1_ADIV_DIV_2 1
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#define ADCx_CFG1_ADIV_DIV_4 2
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#define ADCx_CFG1_ADIV_DIV_8 3
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#define ADCx_CFG1_ADIVCLK_BUS_CLOCK 0
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#define ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2 1
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#define ADCx_CFG1_ADIVCLK_BUS_ALTCLK 2
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#define ADCx_CFG1_ADIVCLK_BUS_ADACK 3
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#define ADCx_CFG1_MODE_8_OR_9_BITS 0
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||||||
|
#define ADCx_CFG1_MODE_12_OR_13_BITS 1
|
||||||
|
#define ADCx_CFG1_MODE_10_OR_11_BITS 2
|
||||||
|
#define ADCx_CFG1_MODE_16_BITS 3
|
||||||
|
|
||||||
|
#define ADCx_SC1n_ADCH_DAD0 0
|
||||||
|
#define ADCx_SC1n_ADCH_DAD1 1
|
||||||
|
#define ADCx_SC1n_ADCH_DAD2 2
|
||||||
|
#define ADCx_SC1n_ADCH_DAD3 3
|
||||||
|
#define ADCx_SC1n_ADCH_DADP0 0
|
||||||
|
#define ADCx_SC1n_ADCH_DADP1 1
|
||||||
|
#define ADCx_SC1n_ADCH_DADP2 2
|
||||||
|
#define ADCx_SC1n_ADCH_DADP3 3
|
||||||
|
#define ADCx_SC1n_ADCH_AD4 4
|
||||||
|
#define ADCx_SC1n_ADCH_AD5 5
|
||||||
|
#define ADCx_SC1n_ADCH_AD6 6
|
||||||
|
#define ADCx_SC1n_ADCH_AD7 7
|
||||||
|
#define ADCx_SC1n_ADCH_AD8 8
|
||||||
|
#define ADCx_SC1n_ADCH_AD9 9
|
||||||
|
#define ADCx_SC1n_ADCH_AD10 10
|
||||||
|
#define ADCx_SC1n_ADCH_AD11 11
|
||||||
|
#define ADCx_SC1n_ADCH_AD12 12
|
||||||
|
#define ADCx_SC1n_ADCH_AD13 13
|
||||||
|
#define ADCx_SC1n_ADCH_AD14 14
|
||||||
|
#define ADCx_SC1n_ADCH_AD15 15
|
||||||
|
#define ADCx_SC1n_ADCH_AD16 16
|
||||||
|
#define ADCx_SC1n_ADCH_AD17 17
|
||||||
|
#define ADCx_SC1n_ADCH_AD18 18
|
||||||
|
#define ADCx_SC1n_ADCH_AD19 19
|
||||||
|
#define ADCx_SC1n_ADCH_AD20 20
|
||||||
|
#define ADCx_SC1n_ADCH_AD21 21
|
||||||
|
#define ADCx_SC1n_ADCH_AD22 22
|
||||||
|
#define ADCx_SC1n_ADCH_AD23 23
|
||||||
|
#define ADCx_SC1n_ADCH_TEMP_SENSOR 26
|
||||||
|
#define ADCx_SC1n_ADCH_BANDGAP 27
|
||||||
|
#define ADCx_SC1n_ADCH_VREFSH 29
|
||||||
|
#define ADCx_SC1n_ADCH_VREFSL 30
|
||||||
|
#define ADCx_SC1n_ADCH_DISABLED 31
|
||||||
|
|
||||||
|
#define ADC_DAD0 (1 << ADCx_SC1n_ADCH_DAD0)
|
||||||
|
#define ADC_DAD1 (1 << ADCx_SC1n_ADCH_DAD1)
|
||||||
|
#define ADC_DAD2 (1 << ADCx_SC1n_ADCH_DAD2)
|
||||||
|
#define ADC_DAD3 (1 << ADCx_SC1n_ADCH_DAD3)
|
||||||
|
#define ADC_DADP0 (1 << ADCx_SC1n_ADCH_DADP0)
|
||||||
|
#define ADC_DADP1 (1 << ADCx_SC1n_ADCH_DADP1)
|
||||||
|
#define ADC_DADP2 (1 << ADCx_SC1n_ADCH_DADP2)
|
||||||
|
#define ADC_DADP3 (1 << ADCx_SC1n_ADCH_DADP3)
|
||||||
|
#define ADC_AD4 (1 << ADCx_SC1n_ADCH_AD4)
|
||||||
|
#define ADC_AD5 (1 << ADCx_SC1n_ADCH_AD5)
|
||||||
|
#define ADC_AD6 (1 << ADCx_SC1n_ADCH_AD6)
|
||||||
|
#define ADC_AD7 (1 << ADCx_SC1n_ADCH_AD7)
|
||||||
|
#define ADC_AD8 (1 << ADCx_SC1n_ADCH_AD8)
|
||||||
|
#define ADC_AD9 (1 << ADCx_SC1n_ADCH_AD9)
|
||||||
|
#define ADC_AD10 (1 << ADCx_SC1n_ADCH_AD10)
|
||||||
|
#define ADC_AD11 (1 << ADCx_SC1n_ADCH_AD11)
|
||||||
|
#define ADC_AD12 (1 << ADCx_SC1n_ADCH_AD12)
|
||||||
|
#define ADC_AD13 (1 << ADCx_SC1n_ADCH_AD13)
|
||||||
|
#define ADC_AD14 (1 << ADCx_SC1n_ADCH_AD14)
|
||||||
|
#define ADC_AD15 (1 << ADCx_SC1n_ADCH_AD15)
|
||||||
|
#define ADC_AD16 (1 << ADCx_SC1n_ADCH_AD16)
|
||||||
|
#define ADC_AD17 (1 << ADCx_SC1n_ADCH_AD17)
|
||||||
|
#define ADC_AD18 (1 << ADCx_SC1n_ADCH_AD18)
|
||||||
|
#define ADC_AD19 (1 << ADCx_SC1n_ADCH_AD19)
|
||||||
|
#define ADC_AD20 (1 << ADCx_SC1n_ADCH_AD20)
|
||||||
|
#define ADC_AD21 (1 << ADCx_SC1n_ADCH_AD21)
|
||||||
|
#define ADC_AD22 (1 << ADCx_SC1n_ADCH_AD22)
|
||||||
|
#define ADC_AD23 (1 << ADCx_SC1n_ADCH_AD23)
|
||||||
|
#define ADC_TEMP_SENSOR (1 << ADCx_SC1n_ADCH_TEMP_SENSOR)
|
||||||
|
#define ADC_BANDGAP (1 << ADCx_SC1n_ADCH_BANDGAP)
|
||||||
|
#define ADC_VREFSH (1 << ADCx_SC1n_ADCH_VREFSH)
|
||||||
|
#define ADC_VREFSL (1 << ADCx_SC1n_ADCH_VREFSL)
|
||||||
|
#define ADC_DISABLED (1 << ADCx_SC1n_ADCH_DISABLED)
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Configuration options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC1 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for ADC1 is included.
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#if !defined(KINETIS_ADC_USE_ADC0) || defined(__DOXYGEN__)
|
||||||
|
#define KINETIS_ADC_USE_ADC0 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(KINETIS_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define KINETIS_ADC_IRQ_PRIORITY 5
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if KINETIS_ADC_USE_ADC0 && !KINETIS_HAS_ADC0
|
||||||
|
#error "ADC1 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !KINETIS_ADC_USE_ADC0
|
||||||
|
#error "ADC driver activated but no ADC peripheral assigned"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver data structures and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC sample data type.
|
||||||
|
*/
|
||||||
|
typedef uint16_t adcsample_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Channels number in a conversion group.
|
||||||
|
*/
|
||||||
|
typedef uint16_t adc_channels_num_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Possible ADC failure causes.
|
||||||
|
* @note Error codes are architecture dependent and should not relied
|
||||||
|
* upon.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||||
|
ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
|
||||||
|
} adcerror_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Type of a structure representing an ADC driver.
|
||||||
|
*/
|
||||||
|
typedef struct ADCDriver ADCDriver;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC notification callback type.
|
||||||
|
*
|
||||||
|
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||||
|
* callback
|
||||||
|
* @param[in] buffer pointer to the most recent samples data
|
||||||
|
* @param[in] n number of buffer rows available starting from @p buffer
|
||||||
|
*/
|
||||||
|
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC error callback type.
|
||||||
|
*
|
||||||
|
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||||
|
* callback
|
||||||
|
* @param[in] err ADC error code
|
||||||
|
*/
|
||||||
|
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conversion group configuration structure.
|
||||||
|
* @details This implementation-dependent structure describes a conversion
|
||||||
|
* operation.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
/**
|
||||||
|
* @brief Enables the circular buffer mode for the group.
|
||||||
|
*/
|
||||||
|
bool circular;
|
||||||
|
/**
|
||||||
|
* @brief Number of the analog channels belonging to the conversion group.
|
||||||
|
*/
|
||||||
|
adc_channels_num_t num_channels;
|
||||||
|
/**
|
||||||
|
* @brief Callback function associated to the group or @p NULL.
|
||||||
|
*/
|
||||||
|
adccallback_t end_cb;
|
||||||
|
/**
|
||||||
|
* @brief Error callback or @p NULL.
|
||||||
|
*/
|
||||||
|
adcerrorcallback_t error_cb;
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief Bitmask of channels for ADC conversion.
|
||||||
|
*/
|
||||||
|
uint32_t channel_mask;
|
||||||
|
/**
|
||||||
|
* @brief ADC CFG1 register initialization data.
|
||||||
|
* @note All the required bits must be defined into this field.
|
||||||
|
*/
|
||||||
|
uint32_t cfg1;
|
||||||
|
/**
|
||||||
|
* @brief ADC SC3 register initialization data.
|
||||||
|
* @note All the required bits must be defined into this field.
|
||||||
|
*/
|
||||||
|
uint32_t sc3;
|
||||||
|
} ADCConversionGroup;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Driver configuration structure.
|
||||||
|
* @note It could be empty on some architectures.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
/* Perform first time calibration */
|
||||||
|
bool calibrate;
|
||||||
|
} ADCConfig;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Structure representing an ADC driver.
|
||||||
|
*/
|
||||||
|
struct ADCDriver {
|
||||||
|
/**
|
||||||
|
* @brief Driver state.
|
||||||
|
*/
|
||||||
|
adcstate_t state;
|
||||||
|
/**
|
||||||
|
* @brief Current configuration data.
|
||||||
|
*/
|
||||||
|
const ADCConfig *config;
|
||||||
|
/**
|
||||||
|
* @brief Current samples buffer pointer or @p NULL.
|
||||||
|
*/
|
||||||
|
adcsample_t *samples;
|
||||||
|
/**
|
||||||
|
* @brief Current samples buffer depth or @p 0.
|
||||||
|
*/
|
||||||
|
size_t depth;
|
||||||
|
/**
|
||||||
|
* @brief Current conversion group pointer or @p NULL.
|
||||||
|
*/
|
||||||
|
const ADCConversionGroup *grpp;
|
||||||
|
#if ADC_USE_WAIT || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Waiting thread.
|
||||||
|
*/
|
||||||
|
thread_reference_t thread;
|
||||||
|
#endif
|
||||||
|
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Mutex protecting the peripheral.
|
||||||
|
*/
|
||||||
|
mutex_t mutex;
|
||||||
|
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||||||
|
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||||||
|
ADC_DRIVER_EXT_FIELDS
|
||||||
|
#endif
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief Pointer to the ADCx registers block.
|
||||||
|
*/
|
||||||
|
ADC_TypeDef *adc;
|
||||||
|
/**
|
||||||
|
* @brief Number of samples expected.
|
||||||
|
*/
|
||||||
|
size_t number_of_samples;
|
||||||
|
/**
|
||||||
|
* @brief Current position in the buffer.
|
||||||
|
*/
|
||||||
|
size_t current_index;
|
||||||
|
/**
|
||||||
|
* @brief Current channel index into group channel_mask.
|
||||||
|
*/
|
||||||
|
size_t current_channel;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if KINETIS_ADC_USE_ADC0 && !defined(__DOXYGEN__)
|
||||||
|
extern ADCDriver ADCD1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void adc_lld_init(void);
|
||||||
|
void adc_lld_start(ADCDriver *adcp);
|
||||||
|
void adc_lld_stop(ADCDriver *adcp);
|
||||||
|
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||||
|
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HAL_USE_ADC */
|
||||||
|
|
||||||
|
#endif /* _ADC_LLD_H_ */
|
||||||
|
|
||||||
|
/** @} */
|
Loading…
Reference in New Issue