I2C4 support without BDMA in I2Cv3.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13407 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -199,6 +199,7 @@
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_USE_I2C4 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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@ -206,12 +207,16 @@
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C4_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_I2C4_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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@ -112,6 +112,7 @@ I2CDriver I2CD4;
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#if STM32_I2C_USE_DMA == TRUE
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static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
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#if STM32_I2C4_USE_BDMA == TRUE
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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if (i2cp->is_bdma)
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#endif
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@ -123,6 +124,7 @@ static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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else
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#endif
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#endif /* STM32_I2C4_USE_BDMA == TRUE */
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#if defined(STM32_I2C_DMA_REQUIRED)
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{
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dmaStreamEnable(i2cp->rx.dma);
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@ -132,6 +134,7 @@ static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
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static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
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#if STM32_I2C4_USE_BDMA == TRUE
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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if (i2cp->is_bdma)
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#endif
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@ -143,6 +146,7 @@ static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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else
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#endif
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#endif /* STM32_I2C4_USE_BDMA == TRUE */
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#if defined(STM32_I2C_DMA_REQUIRED)
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{
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dmaStreamEnable(i2cp->tx.dma);
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@ -152,6 +156,7 @@ static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
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static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
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#if STM32_I2C4_USE_BDMA == TRUE
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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if (i2cp->is_bdma)
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#endif
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@ -163,6 +168,7 @@ static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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else
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#endif
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#endif /* STM32_I2C4_USE_BDMA == TRUE */
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#if defined(STM32_I2C_DMA_REQUIRED)
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{
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dmaStreamDisable(i2cp->rx.dma);
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@ -172,6 +178,7 @@ static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
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static inline void i2c_lld_stop_tx_dma(I2CDriver *i2cp) {
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#if STM32_I2C4_USE_BDMA == TRUE
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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if (i2cp->is_bdma)
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#endif
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@ -183,6 +190,7 @@ static inline void i2c_lld_stop_tx_dma(I2CDriver *i2cp) {
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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else
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#endif
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#endif /* STM32_I2C4_USE_BDMA == TRUE */
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#if defined(STM32_I2C_DMA_REQUIRED)
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{
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dmaStreamDisable(i2cp->tx.dma);
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@ -764,8 +772,13 @@ void i2c_lld_init(void) {
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#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
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I2CD4.is_bdma = true;
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#endif
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#if STM32_I2C4_USE_BDMA == TRUE
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I2CD4.rx.bdma = NULL;
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I2CD4.tx.bdma = NULL;
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#else
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I2CD4.rx.dma = NULL;
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I2CD4.tx.dma = NULL;
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#endif
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#endif
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#if defined(STM32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__)
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nvicEnableVector(STM32_I2C4_GLOBAL_NUMBER, STM32_I2C_I2C4_IRQ_PRIORITY);
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@ -904,6 +917,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
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rccEnableI2C4(true);
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#if STM32_I2C_USE_DMA == TRUE
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{
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#if STM32_I2C4_USE_BDMA == TRUE
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i2cp->rx.bdma = bdmaStreamAllocI(STM32_I2C_I2C4_RX_BDMA_STREAM,
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STM32_I2C_I2C4_IRQ_PRIORITY,
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NULL,
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@ -919,6 +933,23 @@ void i2c_lld_start(I2CDriver *i2cp) {
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i2cp->txdmamode |= STM32_BDMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
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bdmaSetRequestSource(i2cp->rx.bdma, STM32_DMAMUX2_I2C4_RX);
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bdmaSetRequestSource(i2cp->tx.bdma, STM32_DMAMUX2_I2C4_TX);
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#else /* STM32_I2C4_USE_BDMA != TRUE */
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i2cp->rx.dma = dmaStreamAllocI(STM32_I2C_I2C4_RX_DMA_STREAM,
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STM32_I2C_I2C4_IRQ_PRIORITY,
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NULL,
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NULL);
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osalDbgAssert(i2cp->rx.dma != NULL, "unable to allocate stream");
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i2cp->tx.dma = dmaStreamAllocI(STM32_I2C_I2C4_TX_DMA_STREAM,
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STM32_I2C_I2C4_IRQ_PRIORITY,
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NULL,
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NULL);
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osalDbgAssert(i2cp->tx.dma != NULL, "unable to allocate stream");
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i2cp->rxdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
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i2cp->txdmamode |= STM32_DMA_CR_PL(STM32_I2C_I2C4_DMA_PRIORITY);
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dmaSetRequestSource(i2cp->rx.dma, STM32_DMAMUX1_I2C4_RX);
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dmaSetRequestSource(i2cp->tx.dma, STM32_DMAMUX1_I2C4_TX);
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#endif /* STM32_I2C4_USE_BDMA != TRUE */
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}
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#endif /* STM32_I2C_USE_DMA == TRUE */
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}
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@ -191,6 +191,27 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks.*/
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#if !defined(STM32_HAS_I2C1)
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#error "STM32_HAS_I2C1 not defined in registry"
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#endif
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#if !defined(STM32_HAS_I2C2)
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#error "STM32_HAS_I2C2 not defined in registry"
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#endif
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#if !defined(STM32_HAS_I2C3)
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#error "STM32_HAS_I2C3 not defined in registry"
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#endif
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#if !defined(STM32_HAS_I2C4)
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#error "STM32_HAS_I2C4 not defined in registry"
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#endif
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#if !defined(STM32_I2C4_USE_BDMA)
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#error "STM32_I2C4_USE_BDMA not defined in registry"
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#endif
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/** @brief error checks */
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#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
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#error "I2C1 not present in the selected device"
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@ -302,6 +323,8 @@
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#endif
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#if STM32_I2C_USE_I2C4
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#if STM32_I2C4_USE_BDMA
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#if !defined(STM32_I2C_I2C4_RX_BDMA_STREAM)
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#error "STM32_I2C_I2C4_RX_BDMA_STREAM not defined"
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#endif
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@ -321,8 +344,34 @@
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#if !STM32_BDMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C4"
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#endif
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#else /* !STM32_I2C4_USE_BDMA */
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#if !defined(STM32_I2C_I2C4_RX_DMA_STREAM)
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#error "STM32_I2C_I2C4_RX_DMA_STREAM not defined"
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#endif
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#if !defined(STM32_I2C_I2C4_TX_DMA_STREAM)
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#error "STM32_I2C_I2C4_TX_DMA_STREAM not defined"
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#endif
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#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C4_RX_DMA_STREAM)
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#error "Invalid DMA stream assigned to I2C4 RX"
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#endif
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#if !STM32_DMA_IS_VALID_STREAM(STM32_I2C_I2C4_TX_DMA_STREAM)
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#error "Invalid DMA stream assigned to I2C4 TX"
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#endif
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#if !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C4_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C4"
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#endif
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#endif /* !STM32_I2C4_USE_BDMA */
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#endif /* STM32_I2C_USE_I2C4 */
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#if STM32_I2C4_USE_BDMA == TRUE
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#if STM32_I2C_USE_I2C1 || STM32_I2C_USE_I2C2 || STM32_I2C_USE_I2C3
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#define STM32_I2C_DMA_REQUIRED
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#if !defined(STM32_DMA_REQUIRED)
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@ -330,12 +379,25 @@
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#endif
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#endif
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#else /* STM32_I2C4_USE_BDMA != TRUE */
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#if STM32_I2C_USE_I2C1 || STM32_I2C_USE_I2C2 || STM32_I2C_USE_I2C3 || STM32_I2C_USE_I2C4
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#define STM32_I2C_DMA_REQUIRED
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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#endif
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#endif /* STM32_I2C4_USE_BDMA != TRUE */
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#if STM32_I2C4_USE_BDMA == TRUE
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#if STM32_I2C_USE_I2C4
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#define STM32_I2C_BDMA_REQUIRED
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#if !defined(STM32_BDMA_REQUIRED)
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#define STM32_BDMA_REQUIRED
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#endif
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#endif
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#endif /* STM32_I2C4_USE_BDMA == TRUE */
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#endif /* STM32_I2C_USE_DMA == TRUE */
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@ -440,11 +502,13 @@ struct I2CDriver {
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*/
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const stm32_dma_stream_t *dma;
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#endif
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#if (STM32_I2C4_USE_BDMA == TRUE) || defined(__DOXYGEN__)
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#if defined(STM32_I2C_BDMA_REQUIRED) || defined(__DOXYGEN__)
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/**
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* @brief Receive BDMA stream.
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*/
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const stm32_bdma_stream_t *bdma;
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#endif
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#endif
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} rx;
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/**
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*/
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const stm32_dma_stream_t *dma;
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#endif
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#if (STM32_I2C4_USE_BDMA == TRUE) || defined(__DOXYGEN__)
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#if defined(STM32_I2C_BDMA_REQUIRED) || defined(__DOXYGEN__)
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/**
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* @brief Transmit DMA stream.
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*/
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const stm32_bdma_stream_t *bdma;
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#endif
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#endif
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} tx;
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#else /* STM32_I2C_USE_DMA == FALSE */
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/* Platform capabilities. */
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/*===========================================================================*/
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/* RNG attributes.*/
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#define STM32_HAS_RNG1 TRUE
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/* Cores.*/
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#if defined(STM32H750xx) || defined(STM32H742xx) || \
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defined(STM32H743xx) || defined(STM32H753xx)
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* @name STM32H7xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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/* RNG attributes.*/
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#define STM32_HAS_RNG1 TRUE
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/* I2C attributes.*/
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#define STM32_I2C4_USE_BDMA TRUE
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/*===========================================================================*/
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/* STM32H743xx, STM32H753xx, STM32H745xx, STM32H755xx, STM32H747xx, */
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/* STM32H757xx. */
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#define STM32_HAS_CRYP1 FALSE
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#endif
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/* I2C attributes.*/
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#define STM32_I2C4_USE_BDMA FALSE
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/*===========================================================================*/
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/* STM32L4yyxx+. */
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/*===========================================================================*/
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#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
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#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
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#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
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#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
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#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
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#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
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#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
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#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
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#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
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#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
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#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
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/*
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