git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6393 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -154,8 +154,6 @@ void stm32_clock_init(void) {
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/* PWR initialization.*/
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/* PWR initialization.*/
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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PWR->CR = STM32_VOS;
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PWR->CR = STM32_VOS;
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while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
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; /* Waits until power regulator is stable. */
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#else
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#else
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PWR->CR = 0;
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PWR->CR = 0;
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#endif
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#endif
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@ -192,6 +190,11 @@ void stm32_clock_init(void) {
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STM32_PLLM;
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STM32_PLLM;
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RCC->CR |= RCC_CR_PLLON;
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RCC->CR |= RCC_CR_PLLON;
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/* Synchronization with voltage regulator stabilization.*/
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#if defined(STM32F4XX)
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while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
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; /* Waits until power regulator is stable. */
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#if STM32_OVERDRIVE_REQUIRED
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#if STM32_OVERDRIVE_REQUIRED
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/* Overdrive activation performed after activating the PLL in order to save
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/* Overdrive activation performed after activating the PLL in order to save
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time as recommended in RM in "Entering Over-drive mode" paragraph.*/
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time as recommended in RM in "Entering Over-drive mode" paragraph.*/
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@ -201,7 +204,8 @@ void stm32_clock_init(void) {
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PWR->CR |= PWR_CR_ODSWEN;
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PWR->CR |= PWR_CR_ODSWEN;
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while (!(PWR->CSR & PWR_CSR_ODSWRDY)
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while (!(PWR->CSR & PWR_CSR_ODSWRDY)
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;
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;
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#endif
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#endif /* STM32_OVERDRIVE_REQUIRED */
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#endif /* defined(STM32F4XX) */
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/* Waiting for PLL lock.*/
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/* Waiting for PLL lock.*/
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while (!(RCC->CR & RCC_CR_PLLRDY))
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while (!(RCC->CR & RCC_CR_PLLRDY))
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