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Fixed bug in L3GD20 set_fullscale method. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9726 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-07-27 21:07:54 +00:00
parent aad8c627a0
commit 7a98764141
2 changed files with 13 additions and 6 deletions
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15
os/ex/ST/l3gd20.c
View File

@ -33,8 +33,6 @@
/* Driver local definitions. */
/*===========================================================================*/
#define PI 3.14159f
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -237,7 +235,7 @@ static msg_t reset_sensivity(void *ip) {
static msg_t set_full_scale(void *ip, l3gd20_fs_t fs) {
float newfs, scale;
unsigned i;
uint8_t i, cr;
if(fs == L3GD20_FS_250DPS) {
newfs = L3GD20_250DPS;
@ -254,7 +252,16 @@ static msg_t set_full_scale(void *ip, l3gd20_fs_t fs) {
if(newfs != ((L3GD20Driver *)ip)->fullscale) {
scale = newfs / ((L3GD20Driver *)ip)->fullscale;
((L3GD20Driver *)ip)->fullscale = newfs;
((L3GD20Driver *)ip)->fullscale = newfs;
/* Updating register.*/
l3gd20SPIReadRegister(((L3GD20Driver *)ip)->config->spip,
L3GD20_AD_CTRL_REG4, 1, &cr);
cr &= ~(L3GD20_CTRL_REG4_FS_MASK);
cr |= fs;
l3gd20SPIWriteRegister(((L3GD20Driver *)ip)->config->spip,
L3GD20_AD_CTRL_REG4, 1, &cr);
/* Scaling sensitivity and bias. Re-calibration is suggested anyway. */
for(i = 0; i < L3GD20_NUMBER_OF_AXES; i++) {
((L3GD20Driver *)ip)->sensitivity[i] *= scale;

4
os/ex/ST/l3gd20.h
View File

@ -59,7 +59,7 @@
/** @} */
/**
* @brief L3GD20 characteristics
* @brief L3GD20 characteristics.
*
* @{
*/
@ -167,7 +167,7 @@
*/
#define L3GD20_CTRL_REG4_MASK 0xF1 /**< L3GD20_CTRL_REG4 mask */
#define L3GD20_CTRL_REG4_SIM (1 << 0) /**< SPI mode */
#define L3GD20_CTRL_REG4_FS_MASK (3 << 4) /**< Full scale mask */
#define L3GD20_CTRL_REG4_FS_MASK 0x30 /**< Full scale field mask */
#define L3GD20_CTRL_REG4_FS0 (1 << 4) /**< Full scale bit 0 */
#define L3GD20_CTRL_REG4_FS1 (1 << 5) /**< Full scale bit 1 */
#define L3GD20_CTRL_REG4_BLE (1 << 6) /**< Big/little endian data */