From 7ad07fde1e537b0938124d7b6e272a9426635fe3 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 28 Jul 2012 09:48:15 +0000
Subject: [PATCH] git-svn-id:
 svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4482
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32/i2c_lld.c | 38 ++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c
index fee18ab71..dd46c1855 100644
--- a/os/hal/platforms/STM32/i2c_lld.c
+++ b/os/hal/platforms/STM32/i2c_lld.c
@@ -212,11 +212,14 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
                 "Invalid standard mode duty cycle");
 
     /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
+    chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
+                "i2c_lld_set_clock(), #2",
+                "PCLK1 must be divided without remainder");
     clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
 
-    /* Clock divider values under four are not allowed.*/
-    if (clock_div < 0x04)
-      clock_div = 0x04;
+    chDbgAssert(clock_div >= 0x04,
+                "i2c_lld_set_clock(), #3",
+                "Clock divider less then 0x04 not allowed");
     regCCR |= (clock_div & I2C_CCR_CCR);
 
     /* Sets the Maximum Rise Time for standard mode.*/
@@ -225,21 +228,28 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
   else if (clock_speed <= 400000) {
     /* Configure clock_div in fast mode.*/
     chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9),
-                "i2c_lld_set_clock(), #2",
+                "i2c_lld_set_clock(), #4",
                 "Invalid fast mode duty cycle");
 
     if (duty == FAST_DUTY_CYCLE_2) {
       /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
+      chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
+                  "i2c_lld_set_clock(), #5",
+                  "PCLK1 must be divided without remainder");
       clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
     }
     else if (duty == FAST_DUTY_CYCLE_16_9) {
       /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
+      chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
+                  "i2c_lld_set_clock(), #6",
+                  "PCLK1 must be divided without remainder");
       clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
       regCCR |= I2C_CCR_DUTY;
     }
-    /* Clock divider values under one are not allowed.*/
-    if (clock_div < 0x01)
-      clock_div = 0x01;
+
+    chDbgAssert(clock_div >= 0x01,
+                    "i2c_lld_set_clock(), #7",
+                    "Clock divider less then 0x04 not allowed");
     regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
 
     /* Sets the Maximum Rise Time for fast mode.*/
@@ -247,7 +257,7 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
   }
 
   chDbgAssert((clock_div <= I2C_CCR_CCR),
-              "i2c_lld_set_clock(), #3", "the selected clock is too low");
+              "i2c_lld_set_clock(), #8", "the selected clock is too low");
 
   dp->CCR = regCCR;
 }
@@ -797,7 +807,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
      is completed, alternatively for a timeout condition.*/
   while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
     chSysLock();
-    if (!chVTIsArmedI(&vt))
+    if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
       return RDY_TIMEOUT;
     chSysUnlock();
   }
@@ -807,7 +817,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
   /* Atomic check on the timer in order to make sure that a timeout didn't
      happen outside the critical zone.*/
-  if (!chVTIsArmedI(&vt))
+  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
     return RDY_TIMEOUT;
 
   /* Starts the operation.*/
@@ -817,7 +827,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
   /* Waits for the operation completion or a timeout.*/
   i2cp->thread = chThdSelf();
   chSchGoSleepS(THD_STATE_SUSPENDED);
-  if (chVTIsArmedI(&vt))
+  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
     chVTResetI(&vt);
 
   return chThdSelf()->p_u.rdymsg;
@@ -881,7 +891,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
      is completed, alternatively for a timeout condition.*/
   while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
     chSysLock();
-    if (!chVTIsArmedI(&vt))
+    if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
       return RDY_TIMEOUT;
     chSysUnlock();
   }
@@ -891,7 +901,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
   /* Atomic check on the timer in order to make sure that a timeout didn't
      happen outside the critical zone.*/
-  if (!chVTIsArmedI(&vt))
+  if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
     return RDY_TIMEOUT;
 
   /* Starts the operation.*/
@@ -901,7 +911,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
   /* Waits for the operation completion or a timeout.*/
   i2cp->thread = chThdSelf();
   chSchGoSleepS(THD_STATE_SUSPENDED);
-  if (chVTIsArmedI(&vt))
+  if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
     chVTResetI(&vt);
 
   return chThdSelf()->p_u.rdymsg;