Initial SB rework.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15097 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -23,10 +23,10 @@
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#include "oslib_test_root.h"
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/* Static memory areas used by sandboxes.*/
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extern uint32_t __flash1_base__, __flash1_end__,
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__flash2_base__, __flash2_end__,
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__ram1_base__, __ram1_end__,
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__ram2_base__, __ram2_end__;
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extern uint8_t __flash1_base__, __flash1_size__,
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__flash2_base__, __flash2_size__,
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__ram1_base__, __ram1_size__,
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__ram2_base__, __ram2_size__;
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/* Sandbox 1 configuration.*/
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static const sb_config_t sb_config1 = {
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@ -34,10 +34,10 @@ static const sb_config_t sb_config1 = {
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.data_region = 1U,
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.regions = {
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[0] = {
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(uint32_t)&__flash1_base__, (uint32_t)&__flash1_end__, false
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{(uint8_t *)&__flash1_base__, (size_t)&__flash1_size__}, false
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},
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[1] = {
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(uint32_t)&__ram1_base__, (uint32_t)&__ram1_end__, true
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{(uint8_t *)&__ram1_base__, (size_t)&__ram1_size__}, true
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}
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},
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.mpuregs = {
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@ -65,10 +65,10 @@ static const sb_config_t sb_config2 = {
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.data_region = 1U,
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.regions = {
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[0] = {
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(uint32_t)&__flash2_base__, (uint32_t)&__flash2_end__, false
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{(uint8_t *)&__flash2_base__, (size_t)&__flash2_size__}, false
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},
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[1] = {
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(uint32_t)&__ram2_base__, (uint32_t)&__ram2_end__, true
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{(uint8_t *)&__ram2_base__, (size_t)&__ram2_size__}, true
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}
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},
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.mpuregs = {
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@ -23,10 +23,10 @@
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#include "oslib_test_root.h"
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/* Static memory areas used by sandboxes.*/
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extern uint32_t __flash1_base__, __flash1_end__,
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__flash2_base__, __flash2_end__,
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__ram1_base__, __ram1_end__,
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__ram2_base__, __ram2_end__;
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extern uint8_t __flash1_base__, __flash1_size__,
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__flash2_base__, __flash2_size__,
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__ram1_base__, __ram1_size__,
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__ram2_base__, __ram2_size__;
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/* Sandbox 1 configuration.*/
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static const sb_config_t sb_config1 = {
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@ -34,10 +34,10 @@ static const sb_config_t sb_config1 = {
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.data_region = 1U,
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.regions = {
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[0] = {
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(uint32_t)&__flash1_base__, (uint32_t)&__flash1_end__, false
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{(uint8_t *)&__flash1_base__, (size_t)&__flash1_size__}, false
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},
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[1] = {
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(uint32_t)&__ram1_base__, (uint32_t)&__ram1_end__, true
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{(uint8_t *)&__ram1_base__, (size_t)&__ram1_size__}, true
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}
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},
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.stdin_stream = (SandboxStream *)&LPSD1,
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@ -51,10 +51,10 @@ static const sb_config_t sb_config2 = {
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.data_region = 1U,
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.regions = {
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[0] = {
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(uint32_t)&__flash2_base__, (uint32_t)&__flash2_end__, false
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{(uint8_t *)&__flash2_base__, (size_t)&__flash2_size__}, false
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},
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[1] = {
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(uint32_t)&__ram2_base__, (uint32_t)&__ram2_end__, true
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{(uint8_t *)&__ram2_base__, (size_t)&__ram2_size__}, true
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}
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},
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.stdin_stream = (SandboxStream *)&LPSD1,
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@ -49,7 +49,7 @@
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/**
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* @brief Safety Extensions version string.
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*/
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#define CH_SB_VERSION "2.0.0"
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#define CH_SB_VERSION "2.1.0"
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/**
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* @brief Safety Extensions version major number.
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/**
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* @brief Safety Extensions version minor number.
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*/
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#define CH_SB_MINOR 0
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#define CH_SB_MINOR 1
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/**
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* @brief Safety Extensions version patch number.
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@ -109,6 +109,10 @@
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#error "SandBox requires CH_CFG_INTERVALS_SIZE == 32"
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#endif
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#if CH_CFG_USE_MEMCHECKS == FALSE
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#error "SandBox requires CH_CFG_USE_MEMCHECKS == TRUE"
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#endif
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#if PORT_USE_SYSCALL == FALSE
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#error "SandBox requires PORT_USE_SYSCALL == TRUE"
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#endif
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@ -61,8 +61,7 @@ bool sb_is_valid_read_range(sb_class_t *sbcp, const void *start, size_t size) {
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const sb_memory_region_t *rp = &sbcp->config->regions[0];
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do {
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if (((uint32_t)start >= rp->base) && ((uint32_t)start < rp->end) &&
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(size <= ((size_t)rp->base - (size_t)start))) {
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if (chMemIsAreaContainedX(&rp->area, start, size)) {
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return true;
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}
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rp++;
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@ -75,8 +74,7 @@ bool sb_is_valid_write_range(sb_class_t *sbcp, void *start, size_t size) {
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const sb_memory_region_t *rp = &sbcp->config->regions[0];
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do {
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if (((uint32_t)start >= rp->base) && ((uint32_t)start < rp->end) &&
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(size <= ((size_t)rp->base - (size_t)start))) {
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if (chMemIsAreaContainedX(&rp->area, start, size)) {
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return rp->writeable;
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}
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rp++;
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@ -119,7 +117,7 @@ thread_t *sbStartThread(sb_class_t *sbcp, const sb_config_t *config,
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const sb_header_t *sbhp;
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/* Header location.*/
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sbhp = (const sb_header_t *)config->regions[config->code_region].base;
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sbhp = (const sb_header_t *)(void *)config->regions[config->code_region].area.base;
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/* Checking header magic numbers.*/
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if ((sbhp->hdr_magic1 != SB_MAGIC1) || (sbhp->hdr_magic2 != SB_MAGIC2)) {
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@ -139,9 +137,10 @@ thread_t *sbStartThread(sb_class_t *sbcp, const sb_config_t *config,
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.wbase = (stkalign_t *)wsp,
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.wend = (stkalign_t *)wsp + (size / sizeof (stkalign_t)),
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.prio = prio,
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.u_pc = (config->regions[config->code_region].base +
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sizeof (sb_header_t)) | 1U,
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.u_psp = config->regions[config->data_region].end,
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.u_pc = (uint32_t)(config->regions[config->code_region].area.base +
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sizeof (sb_header_t)) | 1U,
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.u_psp = (uint32_t)(config->regions[config->data_region].area.base +
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config->regions[config->data_region].area.size),
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.arg = (void *)sbcp
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};
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#if PORT_SWITCHED_REGIONS_NUMBER > 0
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@ -72,15 +72,9 @@ typedef struct {
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*/
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typedef struct {
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/**
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* @brief Memory range base.
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* @note Zero if not used.
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* @brief Associated memory area.
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*/
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uint32_t base;
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/**
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* @brief Memory range end (non inclusive).
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* @note Zero if not used.
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*/
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uint32_t end;
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memory_region_t area;
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/**
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* @brief Writable memory range.
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*/
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