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ChibiOS
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Initial SB rework. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15097 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-11-16 17:45:29 +00:00
parent 7fc46705c1
commit 7bd05fc08f
5 changed files with 31 additions and 34 deletions
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16
demos/STM32/RT-STM32G474RE-NUCLEO64-SB_HOST_DYNAMIC/main.c
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@ -23,10 +23,10 @@
#include "oslib_test_root.h" #include "oslib_test_root.h"
/* Static memory areas used by sandboxes.*/ /* Static memory areas used by sandboxes.*/
extern uint32_t __flash1_base__, __flash1_end__, extern uint8_t __flash1_base__, __flash1_size__,
__flash2_base__, __flash2_end__, __flash2_base__, __flash2_size__,
__ram1_base__, __ram1_end__, __ram1_base__, __ram1_size__,
__ram2_base__, __ram2_end__; __ram2_base__, __ram2_size__;
/* Sandbox 1 configuration.*/ /* Sandbox 1 configuration.*/
static const sb_config_t sb_config1 = { static const sb_config_t sb_config1 = {
@ -34,10 +34,10 @@ static const sb_config_t sb_config1 = {
.data_region = 1U, .data_region = 1U,
.regions = { .regions = {
[0] = { [0] = {
(uint32_t)&__flash1_base__, (uint32_t)&__flash1_end__, false {(uint8_t *)&__flash1_base__, (size_t)&__flash1_size__}, false
}, },
[1] = { [1] = {
(uint32_t)&__ram1_base__, (uint32_t)&__ram1_end__, true {(uint8_t *)&__ram1_base__, (size_t)&__ram1_size__}, true
} }
}, },
.mpuregs = { .mpuregs = {
@ -65,10 +65,10 @@ static const sb_config_t sb_config2 = {
.data_region = 1U, .data_region = 1U,
.regions = { .regions = {
[0] = { [0] = {
(uint32_t)&__flash2_base__, (uint32_t)&__flash2_end__, false {(uint8_t *)&__flash2_base__, (size_t)&__flash2_size__}, false
}, },
[1] = { [1] = {
(uint32_t)&__ram2_base__, (uint32_t)&__ram2_end__, true {(uint8_t *)&__ram2_base__, (size_t)&__ram2_size__}, true
} }
}, },
.mpuregs = { .mpuregs = {

16
demos/STM32/RT-STM32G474RE-NUCLEO64-SB_HOST_STATIC/main.c
View File

@ -23,10 +23,10 @@
#include "oslib_test_root.h" #include "oslib_test_root.h"
/* Static memory areas used by sandboxes.*/ /* Static memory areas used by sandboxes.*/
extern uint32_t __flash1_base__, __flash1_end__, extern uint8_t __flash1_base__, __flash1_size__,
__flash2_base__, __flash2_end__, __flash2_base__, __flash2_size__,
__ram1_base__, __ram1_end__, __ram1_base__, __ram1_size__,
__ram2_base__, __ram2_end__; __ram2_base__, __ram2_size__;
/* Sandbox 1 configuration.*/ /* Sandbox 1 configuration.*/
static const sb_config_t sb_config1 = { static const sb_config_t sb_config1 = {
@ -34,10 +34,10 @@ static const sb_config_t sb_config1 = {
.data_region = 1U, .data_region = 1U,
.regions = { .regions = {
[0] = { [0] = {
(uint32_t)&__flash1_base__, (uint32_t)&__flash1_end__, false {(uint8_t *)&__flash1_base__, (size_t)&__flash1_size__}, false
}, },
[1] = { [1] = {
(uint32_t)&__ram1_base__, (uint32_t)&__ram1_end__, true {(uint8_t *)&__ram1_base__, (size_t)&__ram1_size__}, true
} }
}, },
.stdin_stream = (SandboxStream *)&LPSD1, .stdin_stream = (SandboxStream *)&LPSD1,
@ -51,10 +51,10 @@ static const sb_config_t sb_config2 = {
.data_region = 1U, .data_region = 1U,
.regions = { .regions = {
[0] = { [0] = {
(uint32_t)&__flash2_base__, (uint32_t)&__flash2_end__, false {(uint8_t *)&__flash2_base__, (size_t)&__flash2_size__}, false
}, },
[1] = { [1] = {
(uint32_t)&__ram2_base__, (uint32_t)&__ram2_end__, true {(uint8_t *)&__ram2_base__, (size_t)&__ram2_size__}, true
} }
}, },
.stdin_stream = (SandboxStream *)&LPSD1, .stdin_stream = (SandboxStream *)&LPSD1,

8
os/sb/host/sb.h
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@ -49,7 +49,7 @@
/** /**
* @brief Safety Extensions version string. * @brief Safety Extensions version string.
*/ */
#define CH_SB_VERSION "2.0.0" #define CH_SB_VERSION "2.1.0"
/** /**
* @brief Safety Extensions version major number. * @brief Safety Extensions version major number.
@ -59,7 +59,7 @@
/** /**
* @brief Safety Extensions version minor number. * @brief Safety Extensions version minor number.
*/ */
#define CH_SB_MINOR 0 #define CH_SB_MINOR 1
/** /**
* @brief Safety Extensions version patch number. * @brief Safety Extensions version patch number.
@ -109,6 +109,10 @@
#error "SandBox requires CH_CFG_INTERVALS_SIZE == 32" #error "SandBox requires CH_CFG_INTERVALS_SIZE == 32"
#endif #endif
#if CH_CFG_USE_MEMCHECKS == FALSE
#error "SandBox requires CH_CFG_USE_MEMCHECKS == TRUE"
#endif
#if PORT_USE_SYSCALL == FALSE #if PORT_USE_SYSCALL == FALSE
#error "SandBox requires PORT_USE_SYSCALL == TRUE" #error "SandBox requires PORT_USE_SYSCALL == TRUE"
#endif #endif

15
os/sb/host/sbhost.c
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@ -61,8 +61,7 @@ bool sb_is_valid_read_range(sb_class_t *sbcp, const void *start, size_t size) {
const sb_memory_region_t *rp = &sbcp->config->regions[0]; const sb_memory_region_t *rp = &sbcp->config->regions[0];
do { do {
if (((uint32_t)start >= rp->base) && ((uint32_t)start < rp->end) && if (chMemIsAreaContainedX(&rp->area, start, size)) {
(size <= ((size_t)rp->base - (size_t)start))) {
return true; return true;
} }
rp++; rp++;
@ -75,8 +74,7 @@ bool sb_is_valid_write_range(sb_class_t *sbcp, void *start, size_t size) {
const sb_memory_region_t *rp = &sbcp->config->regions[0]; const sb_memory_region_t *rp = &sbcp->config->regions[0];
do { do {
if (((uint32_t)start >= rp->base) && ((uint32_t)start < rp->end) && if (chMemIsAreaContainedX(&rp->area, start, size)) {
(size <= ((size_t)rp->base - (size_t)start))) {
return rp->writeable; return rp->writeable;
} }
rp++; rp++;
@ -119,7 +117,7 @@ thread_t *sbStartThread(sb_class_t *sbcp, const sb_config_t *config,
const sb_header_t *sbhp; const sb_header_t *sbhp;
/* Header location.*/ /* Header location.*/
sbhp = (const sb_header_t *)config->regions[config->code_region].base; sbhp = (const sb_header_t *)(void *)config->regions[config->code_region].area.base;
/* Checking header magic numbers.*/ /* Checking header magic numbers.*/
if ((sbhp->hdr_magic1 != SB_MAGIC1) || (sbhp->hdr_magic2 != SB_MAGIC2)) { if ((sbhp->hdr_magic1 != SB_MAGIC1) || (sbhp->hdr_magic2 != SB_MAGIC2)) {
@ -139,9 +137,10 @@ thread_t *sbStartThread(sb_class_t *sbcp, const sb_config_t *config,
.wbase = (stkalign_t *)wsp, .wbase = (stkalign_t *)wsp,
.wend = (stkalign_t *)wsp + (size / sizeof (stkalign_t)), .wend = (stkalign_t *)wsp + (size / sizeof (stkalign_t)),
.prio = prio, .prio = prio,
.u_pc = (config->regions[config->code_region].base + .u_pc = (uint32_t)(config->regions[config->code_region].area.base +
sizeof (sb_header_t)) | 1U, sizeof (sb_header_t)) | 1U,
.u_psp = config->regions[config->data_region].end, .u_psp = (uint32_t)(config->regions[config->data_region].area.base +
config->regions[config->data_region].area.size),
.arg = (void *)sbcp .arg = (void *)sbcp
}; };
#if PORT_SWITCHED_REGIONS_NUMBER > 0 #if PORT_SWITCHED_REGIONS_NUMBER > 0

10
os/sb/host/sbhost.h
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@ -72,15 +72,9 @@ typedef struct {
*/ */
typedef struct { typedef struct {
/** /**
* @brief Memory range base. * @brief Associated memory area.
* @note Zero if not used.
*/ */
uint32_t base; memory_region_t area;
/**
* @brief Memory range end (non inclusive).
* @note Zero if not used.
*/
uint32_t end;
/** /**
* @brief Writable memory range. * @brief Writable memory range.
*/ */