diff --git a/readme.txt b/readme.txt
index fa5088a72..6424696ce 100644
--- a/readme.txt
+++ b/readme.txt
@@ -113,6 +113,8 @@
 - RT:  Merged RT4.
 - NIL: Merged NIL2.
 - NIL: Added STM32F7 demo.
+- HAL: Fixed wrong comments and indents in STM32F7xx-GPT-ADC and 
+       STM32L4-GPT-ADC demos (bug #747).
 - HAL: Fixed wrong comments and indent in STM32F4xx and STM32F7xx 
        hal_lld.h (bug #746).
 - HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745).
diff --git a/testhal/STM32/STM32F7xx/GPT-ADC/main.c b/testhal/STM32/STM32F7xx/GPT-ADC/main.c
index 643fd2114..b7a505152 100644
--- a/testhal/STM32/STM32F7xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32F7xx/GPT-ADC/main.c
@@ -29,10 +29,10 @@
  * GPT4 configuration. This timer is used as trigger for the ADC.
  */
 static const GPTConfig gpt4cfg1 = {
-  frequency:    1000000U,
-  callback:     NULL,
-  cr2:          TIM_CR2_MMS_1,  /* MMS = 010 = TRGO on Update Event.        */
-  dier:         0U
+  .frequency =  1000000U,
+  .callback  =  NULL,
+  .cr2       =  TIM_CR2_MMS_1,  /* MMS = 010 = TRGO on Update Event.        */
+  .dier      =  0U
 };
 
 /*===========================================================================*/
@@ -79,7 +79,7 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
 }
 
 /*
- * ADC errors callbaack, should never happen.
+ * ADC errors callback, should never happen.
  */
 static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
 
@@ -98,13 +98,15 @@ static const ADCConversionGroup adcgrpcfg1 = {
   ADC_GRP1_NUM_CHANNELS,
   adccallback,
   adcerrorcallback,
-  0,                                                    /* CR1 */
-  ADC_CR2_EXTEN_RISING | ADC_CR2_EXTSEL_SRC(12),        /* CR2 */
-  ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144),
+  0,                                                    /* CR1   */
+  ADC_CR2_EXTEN_RISING | ADC_CR2_EXTSEL_SRC(12),        /* CR2   */
+  ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | 
+  ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144),                   /* SMPR1 */
   0,                                                    /* SMPR2 */
-  ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),               /* SQR1 */
-  0,                                                    /* SQR1 */
-  ADC_SQR3_SQ2_N(ADC_CHANNEL_SENSOR) | ADC_SQR3_SQ1_N(ADC_CHANNEL_VREFINT)
+  ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),               /* SQR1  */
+  0,                                                    /* SQR2  */
+  ADC_SQR3_SQ2_N(ADC_CHANNEL_SENSOR) | 
+  ADC_SQR3_SQ1_N(ADC_CHANNEL_VREFINT)                   /* SQR3  */
 };
 
 /*===========================================================================*/
diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/main.c b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
index bddfa5f21..bf843263c 100644
--- a/testhal/STM32/STM32L4xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
@@ -25,10 +25,10 @@
  * GPT4 configuration. This timer is used as trigger for the ADC.
  */
 static const GPTConfig gpt4cfg1 = {
-  frequency:    1000000U,
-  callback:     NULL,
-  cr2:          TIM_CR2_MMS_1,  /* MMS = 010 = TRGO on Update Event.        */
-  dier:         0U
+  .frequency =  1000000U,
+  .callback  =  NULL,
+  .cr2       =  TIM_CR2_MMS_1,  /* MMS = 010 = TRGO on Update Event.        */
+  .dier      =  0U
 };
 
 /*===========================================================================*/
@@ -58,7 +58,7 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
 }
 
 /*
- * ADC errors callbaack, should never happen.
+ * ADC errors callback, should never happen.
  */
 static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
 
@@ -77,13 +77,13 @@ static const ADCConversionGroup adcgrpcfg1 = {
   ADC_GRP1_NUM_CHANNELS,
   adccallback,
   adcerrorcallback,
-  ADC_CFGR_CONT | ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(12), /* CFGR */
-  ADC_TR(0, 4095),                                          /* TR1      */
-  {                                                         /* SMPR[2]  */
+  ADC_CFGR_CONT | ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(12), /* CFGR   */
+  ADC_TR(0, 4095),                                                 /* TR1    */
+  {                                                                /* SMPR[2]*/
     ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5),
     ADC_SMPR1_SMP_AN2(ADC_SMPR_SMP_247P5)
   },
-  {                                                         /* SQR[4]   */
+  {                                                                /* SQR[4] */
     ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN2),
     0,
     0,