From 7e028e11ca99fc141c1a77523b1eae42ba5acce6 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sat, 18 Sep 2021 08:39:22 +0000 Subject: [PATCH] More templates. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14788 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../conf/mcuconf_stm32g0b1xx/mcuconf.h.ftl | 315 ++++++++++++++++++ tools/updater/update_mcuconf_stm32g071xx.sh | 2 +- tools/updater/update_mcuconf_stm32g0b1xx.sh | 29 ++ tools/updater/update_mcuconf_stm32l4rxxx.sh | 2 +- 4 files changed, 346 insertions(+), 2 deletions(-) create mode 100644 tools/ftl/processors/conf/mcuconf_stm32g0b1xx/mcuconf.h.ftl create mode 100644 tools/updater/update_mcuconf_stm32g0b1xx.sh diff --git a/tools/ftl/processors/conf/mcuconf_stm32g0b1xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32g0b1xx/mcuconf.h.ftl new file mode 100644 index 000000000..5628d6c32 --- /dev/null +++ b/tools/ftl/processors/conf/mcuconf_stm32g0b1xx/mcuconf.h.ftl @@ -0,0 +1,315 @@ +[#ftl] +[#-- + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[@pp.changeOutputFile name="mcuconf.h" /] +/* +[@license.EmitLicenseAsText /] +*/ + +/* + * STM32G0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define STM32G0xx_MCUCONF +#define STM32G0B1_MCUCONF +#define STM32G0C1_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"} +#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"} +#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"} +#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)"} +#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWUL)"} +#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"} +#define STM32_PWR_PUCRA ${doc.STM32_PWR_PUCRA!"(0U)"} +#define STM32_PWR_PDCRA ${doc.STM32_PWR_PDCRA!"(0U)"} +#define STM32_PWR_PUCRB ${doc.STM32_PWR_PUCRB!"(0U)"} +#define STM32_PWR_PDCRB ${doc.STM32_PWR_PDCRB!"(0U)"} +#define STM32_PWR_PUCRC ${doc.STM32_PWR_PUCRC!"(0U)"} +#define STM32_PWR_PDCRC ${doc.STM32_PWR_PDCRC!"(0U)"} +#define STM32_PWR_PUCRD ${doc.STM32_PWR_PUCRD!"(0U)"} +#define STM32_PWR_PDCRD ${doc.STM32_PWR_PDCRD!"(0U)"} +#define STM32_PWR_PUCRE ${doc.STM32_PWR_PUCRE!"(0U)"} +#define STM32_PWR_PDCRE ${doc.STM32_PWR_PDCRE!"(0U)"} +#define STM32_PWR_PUCRF ${doc.STM32_PWR_PUCRF!"(0U)"} +#define STM32_PWR_PDCRF ${doc.STM32_PWR_PDCRF!"(0U)"} +#define STM32_HSIDIV_VALUE ${doc.STM32_HSIDIV_VALUE!"1"} +#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"} +#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"} +#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"} +#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"} +#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLLRCLK"} +#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSI16"} +#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"2"} +#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"16"} +#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"} +#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"4"} +#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"2"} +#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"} +#define STM32_PPRE ${doc.STM32_PPRE!"STM32_PPRE_DIV1"} +#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"} +#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"} +#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"} + +/* + * Peripherals clocks and sources. + */ +#define STM32_USBSEL ${doc.STM32_USBSEL!"STM32_USBSEL_PLLQCLK"} +#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"} +#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"} +#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"} +#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"} +#define STM32_LPUART2SEL ${doc.STM32_LPUART2SEL!"STM32_LPUART2SEL_SYSCLK"} +#define STM32_CECSEL ${doc.STM32_CECSEL!"STM32_CECSEL_HSI16DIV"} +#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK"} +#define STM32_I2S1SEL ${doc.STM32_I2S1SEL!"STM32_I2S1SEL_SYSCLK"} +#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK"} +#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK"} +#define STM32_TIM1SEL ${doc.STM32_TIM1SEL!"STM32_TIM1SEL_TIMPCLK"} +#define STM32_TIM15SEL ${doc.STM32_TIM15SEL!"STM32_TIM15SEL_TIMPCLK"} +#define STM32_RNGSEL ${doc.STM32_RNGSEL!"STM32_RNGSEL_HSI16"} +#define STM32_RNGDIV_VALUE ${doc.STM32_RNGDIV_VALUE!"1"} +#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_PLLPCLK"} +#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_NOCLOCK"} + +/* + * Shared IRQ settings. + */ +#define STM32_IRQ_EXTI0_1_PRIORITY ${doc.STM32_IRQ_EXTI0_1_PRIORITY!"3"} +#define STM32_IRQ_EXTI2_3_PRIORITY ${doc.STM32_IRQ_EXTI2_3_PRIORITY!"3"} +#define STM32_IRQ_EXTI4_15_PRIORITY ${doc.STM32_IRQ_EXTI4_15_PRIORITY!"3"} +#define STM32_IRQ_EXTI1921_PRIORITY ${doc.STM32_IRQ_EXTI1921_PRIORITY!"3"} + +#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"2"} +#define STM32_IRQ_USART2_LP2_PRIORITY ${doc.STM32_IRQ_USART2_LP2_PRIORITY!"2"} +#define STM32_IRQ_USART3_4_5_6_LP1_PRIORITY ${doc.STM32_IRQ_USART3_4_5_6_LP1_PRIORITY!"2"} + +#define STM32_IRQ_TIM1_UP_PRIORITY ${doc.STM32_IRQ_TIM1_UP_PRIORITY!"1"} +#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"1"} +#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"1"} +#define STM32_IRQ_TIM3_4_PRIORITY ${doc.STM32_IRQ_TIM3_4_PRIORITY!"1"} +#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"1"} +#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"1"} +#define STM32_IRQ_TIM14_PRIORITY ${doc.STM32_IRQ_TIM14_PRIORITY!"1"} +#define STM32_IRQ_TIM15_PRIORITY ${doc.STM32_IRQ_TIM15_PRIORITY!"1"} +#define STM32_IRQ_TIM16_PRIORITY ${doc.STM32_IRQ_TIM16_PRIORITY!"1"} +#define STM32_IRQ_TIM17_PRIORITY ${doc.STM32_IRQ_TIM17_PRIORITY!"1"} + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"} +#define STM32_ADC_ADC1_CKMODE ${doc.STM32_ADC_ADC1_CKMODE!"STM32_ADC_CKMODE_ADCCLK"} +#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"} +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"2"} +#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"2"} + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"} +#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"} +#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"} +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"3"} +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"3"} +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"} +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"} +#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"} +#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"} +#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"} +#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"} +#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"} +#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"} +#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"} +#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"} +#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"} +#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"} + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"} +#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"} +#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"} +#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"} +#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"3"} +#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"3"} +#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"} +#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"} +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"} + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"} +#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"} +#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"} +#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"} +#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"} + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"} +#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"} +#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"} +#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"} +#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"} +#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"} +#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"} +#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"} + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"} +#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"} +#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"} +#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"} + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"} +#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"} +#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"} +#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"} +#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"} +#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"} +#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"} +#define STM32_SERIAL_USE_LPUART2 ${doc.STM32_SERIAL_USE_LPUART2!"FALSE"} + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 ${doc.STM32_SIO_USE_USART1!"FALSE"} +#define STM32_SIO_USE_USART2 ${doc.STM32_SIO_USE_USART2!"FALSE"} +#define STM32_SIO_USE_USART3 ${doc.STM32_SIO_USE_USART3!"FALSE"} +#define STM32_SIO_USE_UART4 ${doc.STM32_SIO_USE_UART4!"FALSE"} +#define STM32_SIO_USE_UART5 ${doc.STM32_SIO_USE_UART5!"FALSE"} +#define STM32_SIO_USE_USART6 ${doc.STM32_SIO_USE_USART6!"FALSE"} +#define STM32_SIO_USE_LPUART1 ${doc.STM32_SIO_USE_LPUART1!"FALSE"} +#define STM32_SIO_USE_LPUART2 ${doc.STM32_SIO_USE_LPUART2!"FALSE"} + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"} +#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"} +#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"} +#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"} +#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"} +#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"} +#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"2"} +#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"2"} +#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"2"} +#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"} + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"2"} +#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"} + +/* + * TRNG driver system settings. + * NOTE: STM32G0C1 only. + */ +#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"} + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"} +#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"} +#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"} +#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"} +#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"} +#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"} +#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"} +#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"} +#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"} +#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"} +#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"} +#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"} +#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"} +#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"} + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"FALSE"} +#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"} +#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"} +#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"} + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"} + +#endif /* MCUCONF_H */ diff --git a/tools/updater/update_mcuconf_stm32g071xx.sh b/tools/updater/update_mcuconf_stm32g071xx.sh index c9fff1230..d53878799 100644 --- a/tools/updater/update_mcuconf_stm32g071xx.sh +++ b/tools/updater/update_mcuconf_stm32g071xx.sh @@ -10,7 +10,7 @@ if [ $# -eq 2 ] elif [ $# -eq 1 ] then declare conffile=$(<$1) - if egrep -q "STM32G071_MCUCONF" <<< "$conffile" + if egrep -q "STM32G071_MCUCONF" <<< "$conffile" || egrep -q "STM32G081_MCUCONF" <<< "$conffile" then echo Processing: $1 egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt diff --git a/tools/updater/update_mcuconf_stm32g0b1xx.sh b/tools/updater/update_mcuconf_stm32g0b1xx.sh new file mode 100644 index 000000000..af56408ab --- /dev/null +++ b/tools/updater/update_mcuconf_stm32g0b1xx.sh @@ -0,0 +1,29 @@ +#!/bin/bash +if [ $# -eq 2 ] + then + if [ $1 = "rootpath" ] + then + find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32g0b1xx.sh "{}" \; + else + echo "Usage: update_mcuconf_stm32g0b1xx.sh [rootpath ]" + fi +elif [ $# -eq 1 ] +then + declare conffile=$(<$1) + if egrep -q "STM32G0B1_MCUCONF" <<< "$conffile" || egrep -q "STM32G0C1_MCUCONF" <<< "$conffile" + then + echo Processing: $1 + egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt + if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32g0b1xx + then + echo + echo "aborted" + exit 1 + fi + cp ./mcuconf.h $1 + rm ./mcuconf.h ./values.txt + fi +else + echo "Usage: update_mcuconf_stm32g0b1xx.sh [rootpath ]" + echo " update_mcuconf_stm32g0b1xx.sh ]" +fi diff --git a/tools/updater/update_mcuconf_stm32l4rxxx.sh b/tools/updater/update_mcuconf_stm32l4rxxx.sh index dd99b1cd6..ac602dbbf 100644 --- a/tools/updater/update_mcuconf_stm32l4rxxx.sh +++ b/tools/updater/update_mcuconf_stm32l4rxxx.sh @@ -10,7 +10,7 @@ if [ $# -eq 2 ] elif [ $# -eq 1 ] then declare conffile=$(<$1) - if egrep -q "STM32L4P5_MCUCONF" <<< "$conffile" || "STM32L4Q5_MCUCONF" <<< "$conffile" || "STM32L4R5_MCUCONF" <<< "$conffile" || egrep -q "STM32L4S5_MCUCONF" <<< "$conffile" || egrep -q "STM32L4R7_MCUCONF" <<< "$conffile" || egrep -q "STM32L4S7_MCUCONF" <<< "$conffile" || egrep -q "STM32L4R9_MCUCONF" <<< "$conffile" || egrep -q "STM32L4S9_MCUCONF" <<< "$conffile" + if egrep -q "STM32L4P5_MCUCONF" <<< "$conffile" || egrep -q "STM32L4Q5_MCUCONF" <<< "$conffile" || egrep -q "STM32L4R5_MCUCONF" <<< "$conffile" || egrep -q "STM32L4S5_MCUCONF" <<< "$conffile" || egrep -q "STM32L4R7_MCUCONF" <<< "$conffile" || egrep -q "STM32L4S7_MCUCONF" <<< "$conffile" || egrep -q "STM32L4R9_MCUCONF" <<< "$conffile" || egrep -q "STM32L4S9_MCUCONF" <<< "$conffile" then echo Processing: $1 egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt