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New defaults for H7 clock dividers for higher performance. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13334 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-02-08 11:45:12 +00:00
parent d4bb13cec9
commit 7f1ae50109
7 changed files with 31 additions and 31 deletions
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10
demos/STM32/RT-STM32H743ZI_REV_V-NUCLEO144/cfg/mcuconf.h
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@ -121,11 +121,11 @@
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.

10
testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -121,11 +121,11 @@
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.

10
testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -121,11 +121,11 @@
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.

10
testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
View File

@ -121,11 +121,11 @@
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.

10
testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
View File

@ -121,11 +121,11 @@
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
/*
* Peripherals clocks static settings.

2
testhal/STM32/multi/SPI/debug/STM32-SPI (Select ELF file)(OpenOCD, Flash and Run).launch
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@ -33,7 +33,7 @@
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
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<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;xPSR-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFG1-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFG2-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IER-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;SR-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IFCR-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;TXDR-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RXDR-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRCPOLY-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;TXCRC-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RXCRC-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;UDRDR-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;I2SCFGR-spi-null-spi_thread_1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFG1-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFG2-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IER-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;SR-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IFCR-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;TXDR-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RXDR-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRCPOLY-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;TXCRC-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RXCRC-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;UDRDR-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;I2SCFGR-spi-null-_idle_thread-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x40021004&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${selected_resource_loc}"/>

10
tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
View File

@ -132,11 +132,11 @@
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL1_P_CK"}
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE_CK"}
#define STM32_D1CPRE ${doc.STM32_D1CPRE!"STM32_D1CPRE_DIV1"}
#define STM32_D1HPRE ${doc.STM32_D1HPRE!"STM32_D1HPRE_DIV4"}
#define STM32_D1PPRE3 ${doc.STM32_D1PPRE3!"STM32_D1PPRE3_DIV1"}
#define STM32_D2PPRE1 ${doc.STM32_D2PPRE1!"STM32_D2PPRE1_DIV1"}
#define STM32_D2PPRE2 ${doc.STM32_D2PPRE2!"STM32_D2PPRE2_DIV1"}
#define STM32_D3PPRE4 ${doc.STM32_D3PPRE4!"STM32_D3PPRE4_DIV1"}
#define STM32_D1HPRE ${doc.STM32_D1HPRE!"STM32_D1HPRE_DIV2"}
#define STM32_D1PPRE3 ${doc.STM32_D1PPRE3!"STM32_D1PPRE3_DIV2"}
#define STM32_D2PPRE1 ${doc.STM32_D2PPRE1!"STM32_D2PPRE1_DIV2"}
#define STM32_D2PPRE2 ${doc.STM32_D2PPRE2!"STM32_D2PPRE2_DIV2"}
#define STM32_D3PPRE4 ${doc.STM32_D3PPRE4!"STM32_D3PPRE4_DIV2"}
/*
* Peripherals clocks static settings.