diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h index bd7c939b7..81c9b911f 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h @@ -164,8 +164,6 @@ /* * IRQ system settings. */ -#define STM32_IRQ_MDMA_PRIORITY 9 - #define STM32_IRQ_EXTI0_PRIORITY 6 #define STM32_IRQ_EXTI1_PRIORITY 6 #define STM32_IRQ_EXTI2_PRIORITY 6 @@ -179,6 +177,8 @@ #define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI20_21_PRIORITY 6 +#define STM32_IRQ_MDMA_PRIORITY 9 + #define STM32_IRQ_QUADSPI1_PRIORITY 10 #define STM32_IRQ_TIM1_UP_PRIORITY 7 diff --git a/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.c b/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.c index 9020dc57b..c77bfa0dd 100644 --- a/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.c +++ b/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.c @@ -240,11 +240,6 @@ const stm32_mdma_channel_t *dmaChannelAllocI(uint32_t id, rccEnableMDMA(true); } - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) { - nvicEnableVector(STM32_MDMA_NUMBER, STM32_IRQ_MDMA_PRIORITY); - } - return mdmachp; } } @@ -299,9 +294,6 @@ void mdmaChannelFreeI(const stm32_mdma_channel_t *mdmachp) { osalDbgAssert((mdma.allocated_mask & (1U << channel)) != 0U, "not allocated"); - /* Disables the associated IRQ vector.*/ - nvicDisableVector(STM32_MDMA_NUMBER); - /* Marks the channel as not allocated.*/ mdma.allocated_mask &= ~(1U << channel); diff --git a/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.h b/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.h index 09a923f28..6dfe9ebab 100644 --- a/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.h +++ b/os/hal/ports/STM32/LLD/MDMAv1/stm32_mdma.h @@ -207,7 +207,9 @@ #define STM32_MDMA_CTCR_SWRM (1U << 30) -#define STM32_MDMA_CTCR_BWM (1U << 31) +#define STM32_MDMA_CTCR_BWM_MASK (1U << 31) +#define STM32_MDMA_CTCR_BWM_NON_BUFF (0U << 31) +#define STM32_MDMA_CTCR_BWM_BUFF (1U << 31) /** @} */ /** @@ -380,6 +382,16 @@ typedef struct { (mdmachp)->channel->CCR |= STM32_MDMA_CCR_EN; \ } while (0) +/** + * @brief Channel enable check. + * @pre The stream must have been allocated using @p mdmaChannelAlloc(). + * @post After use the stream can be released using @p mdmaChannelFree(). + * + * @param[in] mdmachp pointer to a stm32_mdma_channel_t structure + */ +#define mdmaChannelIsEnabled(mdmachp) \ + (((mdmachp)->channel->CCR & STM32_MDMA_CCR_EN) != 0U) + /** * @brief MDMA stream interrupt sources clear. * @pre The stream must have been allocated using @p mdmaChannelAlloc(). @@ -396,6 +408,18 @@ typedef struct { STM32_MDMA_CIFCR_CCTCIF | \ STM32_MDMA_CIFCR_CTEIF); \ } while (0) + +/** + * @brief MDMA IRQ enable. + */ +#define mdma_irq_init() \ + nvicEnableVector(STM32_MDMA_NUMBER, STM32_IRQ_MDMA_PRIORITY) + +/** + * @brief MDMA IRQ disable. + */ +#define mdma_irq_deinit() \ + nvicDisableVector(STM32_MDMA_NUMBER) /** @} */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c index dd1e1c404..1b005ad5f 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c @@ -132,14 +132,6 @@ void wspi_lld_init(void) { wspiObjectInit(&WSPID1); WSPID1.qspi = QUADSPI; WSPID1.mdma = NULL; -/* TODO WSPID1.mdmamode = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_WSPI_QUADSPI1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_MINC | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE;*/ - nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_IRQ_QUADSPI1_PRIORITY); #endif } @@ -248,12 +240,26 @@ void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) { */ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp, size_t n, const uint8_t *txbuf) { + uint32_t ctcr = STM32_MDMA_CTCR_BWM_NON_BUFF | /* Dest. non-cacheable. */ + STM32_MDMA_CTCR_TRGM_BUFFER | /* Trigger on buffer. */ + STM32_MDMA_CTCR_TLEN(0U) | /* One byte buffer. */ + STM32_MDMA_CTCR_DBURST_16 | /* Assuming AXI bus. */ + STM32_MDMA_CTCR_SBURST_16 | /* Assuming AXI bus. */ + STM32_MDMA_CTCR_DINCOS_BYTE | /* Byte increment. */ + STM32_MDMA_CTCR_SINCOS_BYTE | /* Byte increment. */ + STM32_MDMA_CTCR_DSIZE_BYTE | /* Destination size. */ + STM32_MDMA_CTCR_SSIZE_BYTE | /* Source size. */ + STM32_MDMA_CTCR_DINC_FIXED | /* Destination fixed. */ + STM32_MDMA_CTCR_SINC_INC; /* Source incremented. */ + uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) | + STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/ + STM32_MDMA_CCR_TCIE; /* On transfer error. */ /* MDMA initializations.*/ mdmaChannelSetSourceX(wspip->mdma, &wspip->qspi->DR); mdmaChannelSetDestinationX(wspip->mdma, txbuf); mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0); - mdmaChannelSetModeX(wspip->mdma, wspip->mdmactcr, wspip->mdmaccr); + mdmaChannelSetModeX(wspip->mdma, ctcr, ccr); wspip->qspi->DLR = n - 1; wspip->qspi->ABR = cmdp->alt; @@ -278,12 +284,26 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp, */ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp, size_t n, uint8_t *rxbuf) { + uint32_t ctcr = STM32_MDMA_CTCR_BWM_NON_BUFF | /* Dest. non-cacheable. */ + STM32_MDMA_CTCR_TRGM_BUFFER | /* Trigger on buffer. */ + STM32_MDMA_CTCR_TLEN(0U) | /* One byte buffer. */ + STM32_MDMA_CTCR_DBURST_16 | /* Assuming AXI bus. */ + STM32_MDMA_CTCR_SBURST_16 | /* Assuming AXI bus. */ + STM32_MDMA_CTCR_DINCOS_BYTE | /* Byte increment. */ + STM32_MDMA_CTCR_SINCOS_BYTE | /* Byte increment. */ + STM32_MDMA_CTCR_DSIZE_BYTE | /* Destination size. */ + STM32_MDMA_CTCR_SSIZE_BYTE | /* Source size. */ + STM32_MDMA_CTCR_DINC_INC | /* Destination incr. */ + STM32_MDMA_CTCR_SINC_FIXED; /* Source fixed. */ + uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) | + STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/ + STM32_MDMA_CCR_TCIE; /* On transfer error. */ /* MDMA initializations.*/ mdmaChannelSetSourceX(wspip->mdma, rxbuf); mdmaChannelSetDestinationX(wspip->mdma, &wspip->qspi->DR); mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0); - mdmaChannelSetModeX(wspip->mdma, wspip->mdmactcr, wspip->mdmaccr); + mdmaChannelSetModeX(wspip->mdma, ctcr, ccr); wspip->qspi->DLR = n - 1; wspip->qspi->ABR = cmdp->alt; diff --git a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h index e1c40862f..50c63466e 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h +++ b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h @@ -250,11 +250,19 @@ /* Pointer to the QUADSPIx registers block.*/ \ QUADSPI_TypeDef *qspi; \ /* QUADSPI MDMA channel.*/ \ - const stm32_mdma_channel_t *mdma; \ - /* QUADSPI MDMA CCR bit mask.*/ \ - uint32_t mdmaccr; \ - /* QUADSPI MDMA CTCR bit mask.*/ \ - uint32_t mdmactcr + const stm32_mdma_channel_t *mdma + +/** + * @brief QUADSPI IRQ enable. + */ +#define quadspi_irq_init() \ + nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_IRQ_QUADSPI1_PRIORITY) + +/** + * @brief QUADSPI IRQ disable. + */ +#define quadspi_irq_deinit() \ + nvicDisableVector(STM32_QUADSPI1_NUMBER) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c index de9b9e81e..5d53420f7 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c @@ -107,6 +107,10 @@ void irqInit(void) { exti19_irq_init(); exti20_exti21_irq_init(); + mdma_irq_init(); + + quadspi_irq_init(); + tim1_irq_init(); tim2_irq_init(); tim3_irq_init(); @@ -146,6 +150,10 @@ void irqDeinit(void) { exti19_irq_deinit(); exti20_exti21_irq_deinit(); + mdma_irq_deinit(); + + quadspi_irq_deinit(); + tim1_irq_deinit(); tim2_irq_deinit(); tim3_irq_deinit(); diff --git a/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl index 151f8c7a6..b705379b0 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl @@ -188,6 +188,10 @@ #define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"} #define STM32_IRQ_EXTI20_21_PRIORITY ${doc.STM32_IRQ_EXTI20_21_PRIORITY!"6"} +#define STM32_IRQ_MDMA_PRIORITY ${doc.STM32_IRQ_MDMA_PRIORITY!"9"} + +#define STM32_IRQ_QUADSPI1_PRIORITY ${doc.STM32_IRQ_QUADSPI1_PRIORITY!"10"} + #define STM32_IRQ_TIM1_UP_PRIORITY ${doc.STM32_IRQ_TIM1_UP_PRIORITY!"7"} #define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"} #define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"} @@ -232,12 +236,8 @@ /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"} -#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"} -#define STM32_CAN_USE_CAN3 ${doc.STM32_CAN_USE_CAN3!"FALSE"} -#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"} -#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"} -#define STM32_CAN_CAN3_IRQ_PRIORITY ${doc.STM32_CAN_CAN3_IRQ_PRIORITY!"11"} +#define STM32_CAN_USE_FDCAN1 ${doc.STM32_CAN_USE_FDCAN1!"FALSE"} +#define STM32_CAN_USE_FDCAN2 ${doc.STM32_CAN_USE_FDCAN2!"FALSE"} /* * DAC driver system settings.