Enabled ARM cycle counter
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11256 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -76,6 +76,15 @@ Boot_Handler:
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ldr r1, =SFR_L2CC_HRAMC
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str r0, [r1]
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b Reset_Handler
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/*
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* Enabling Cycle counter
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*/
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mrc p15, 0, r0, c9, c12, 0 // read PMCR register
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orr r0, r0, #(0x1) // set E bit 0 to enable counter
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mcr p15, 0, r0, c9, c12, 0 // write r0
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mrc p15, 0, r0, c9, c12, 1 // read PMCNTENSET register
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orr r0, r0, #(0x1 << 31) // set bit 31 to enable counter
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mcr p15, 0, r0, c9, c12, 1 // write r0
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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