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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13373 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-02-20 09:38:16 +00:00
parent 0fb8891f18
commit 813ef3b623
43 changed files with 85 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
demos/STM32/NIL-STM32L476-DISCOVERY/cfg/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

2
demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/halconf.h
View File

@ -44,7 +44,7 @@
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC TRUE
#define HAL_USE_ADC FALSE
#endif
/**

4
demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h
View File

@ -50,7 +50,7 @@
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 2
#define STM32_PLLN_VALUE 16
#define STM32_PLLP_VALUE 4
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 4
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
@ -108,7 +108,7 @@
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 1
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.

1
demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
View File

@ -134,6 +134,7 @@
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

2
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
View File

@ -155,6 +155,8 @@
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h
View File

@ -125,6 +125,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h
View File

@ -130,6 +130,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST_DYNAMIC/cfg/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST_STATIC/cfg/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L476RG-NUCLEO64/cfg/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h
View File

@ -152,6 +152,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

29
os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c
View File

@ -57,6 +57,23 @@ ADCDriver ADCD1;
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief ADC voltage regulator enable.
*
* @param[in] adc pointer to the ADC registers block
*/
NOINLINE static void adc_lld_vreg_on(ADC_TypeDef *adc) {
volatile uint32_t loop;
osalDbgAssert(adc->CR == 0, "invalid register state");
adc->CR = ADC_CR_ADVREGEN;
loop = (STM32_HCLK >> 20) << 4;
do {
loop--;
} while (loop > 0);
}
/**
* @brief Stops an ongoing conversion, if any.
*
@ -167,11 +184,13 @@ void adc_lld_init(void) {
ADC->CCR = 0;
#endif
osalDbgAssert(ADC1->CR == 0, "invalid register state");
/* Regulator enabled and stabilized before calibration.*/
adc_lld_vreg_on(ADC1);
ADC1->CR |= ADC_CR_ADCAL;
osalDbgAssert(ADC1->CR != 0, "invalid register state");
while (ADC1->CR & ADC_CR_ADCAL)
;
ADC1->CR = 0;
rccDisableADC1();
}
@ -206,6 +225,9 @@ void adc_lld_start(ADCDriver *adcp) {
}
#endif /* STM32_ADC_USE_ADC1 */
/* Regulator enabled and stabilized before calibration.*/
adc_lld_vreg_on(ADC1);
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR = ADC_CR_ADEN;
@ -244,6 +266,9 @@ void adc_lld_stop(ADCDriver *adcp) {
;
}
/* Regulator and anything else off.*/
adcp->adc->CR = 0;
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp)
rccDisableADC1();

10
os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h
View File

@ -161,7 +161,7 @@
* default, @p STM32_ADC_CKMODE_ADCCLK).
*/
#if !defined(STM32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__)
#define STM32_ADC_PRESCALER_VALUE 1
#define STM32_ADC_PRESCALER_VALUE 2
#endif
#endif
@ -188,6 +188,10 @@
#error "STM32_HAS_ADC1 not defined in registry"
#endif
#if !defined(STM32_ADC_SUPPORTS_PRESCALER)
#error "STM32_ADC_SUPPORTS_PRESCALER not defined in registry"
#endif
#if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_HANDLER))
#error "STM32_ADC1_HANDLER not defined in registry"
#endif
@ -246,9 +250,7 @@
/* ADC clock source checks.*/
#if STM32_ADC_SUPPORTS_PRESCALER == TRUE
#if STM32_ADC_PRESCALER_VALUE == 1
#define STM32_ADC_PRESC 0U
#elif STM32_ADC_PRESCALER_VALUE == 2
#if STM32_ADC_PRESCALER_VALUE == 2
#define STM32_ADC_PRESC 1U
#elif STM32_ADC_PRESCALER_VALUE == 4
#define STM32_ADC_PRESC 2U

8
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -264,7 +264,7 @@
#define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U)
#define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */
#define STM32_ADCSEL_NOCLK (0U << 30U) /**< ADC source is SYSCLK. */
#define STM32_ADCSEL_SYSCLK (0U << 30U) /**< ADC source is SYSCLK. */
#define STM32_ADCSEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */
#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
/** @} */
@ -402,7 +402,7 @@
* @note The allowed values are 2..32.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLP_VALUE 4
#define STM32_PLLP_VALUE 2
#endif
/**
@ -1463,8 +1463,8 @@
/**
* @brief ADC clock frequency.
*/
#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
#define STM32_ADCCLK 0
#if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__)
#define STM32_ADCCLK STM32_SYSCLK
#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK
#define STM32_ADCCLK STM32_PLL_P_CLKOUT
#elif STM32_ADCSEL == STM32_ADCSEL_HSI16

6
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -51,13 +51,13 @@
*/
#if defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \
defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32G04 Access Line"
#define PLATFORM_NAME "STM32G4 Access Line"
#elif defined(STM32G473xx)
#define PLATFORM_NAME "STM32G0 Performance Line"
#define PLATFORM_NAME "STM32G4 Performance Line"
#elif defined(STM32G483xx)
#define PLATFORM_NAME "STM32G0 Performance Line with Crypto"
#define PLATFORM_NAME "STM32G4 Performance Line with Crypto"
#elif defined(STM32G474xx)
#define PLATFORM_NAME "STM32G4 Hi-resolution Line"

1
testex/STM32/STM32L4xx/SPI-L3GD20/cfg/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/STM32L4xx/CAN/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

4
testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/mcuconf.h
View File

@ -50,7 +50,7 @@
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 2
#define STM32_PLLN_VALUE 16
#define STM32_PLLP_VALUE 4
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 4
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
@ -108,7 +108,7 @@
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 1
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.

1
testhal/STM32/multi/ADC/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

4
testhal/STM32/multi/ADC/debug/STM32-ADC (Select ELF file)(OpenOCD, Flash and Run).launch
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File diff suppressed because one or more lines are too long

2
testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h
View File

@ -155,6 +155,8 @@
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/DAC/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/EFL-MFS/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/RTC/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/SPI/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/TRNG/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/WSPI-MFS/cfg/stm32l476_discovery/mcuconf.h
View File

@ -149,6 +149,7 @@
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

1
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -157,6 +157,7 @@
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.

4
tools/ftl/processors/conf/mcuconf_stm32g071xx/mcuconf.h.ftl
View File

@ -61,7 +61,7 @@
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSI16"}
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"2"}
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"16"}
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"4"}
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"4"}
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"2"}
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
@ -119,7 +119,7 @@
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"2"}
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"1"}
#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"2"}
/*
* DAC driver system settings.