git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4027 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
822ca41c6b
commit
81bff0ff66
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@ -56,8 +56,8 @@ typedef struct {
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* @brief Device input endpoint registers group.
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*/
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typedef struct {
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volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint control
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register. */
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volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint
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control register. */
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volatile uint32_t resvd4;
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volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt
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register. */
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@ -74,14 +74,14 @@ typedef struct {
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* @brief Device output endpoint registers group.
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*/
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typedef struct {
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volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint control
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register. */
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volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint
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control register. */
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volatile uint32_t resvd4;
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volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt
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register. */
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volatile uint32_t resvdC;
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volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer size
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register. */
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volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer
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size register. */
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1C;
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@ -103,9 +103,9 @@ typedef struct {
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volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop
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register. */
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volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */
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volatile uint32_t DIEPTXF0; /**< @brief endpoint 0 transmit FIFO size
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volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size
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register. */
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volatile uint32_t HNPTXSTS; /**< @brief non-periodic transmit FIFO/queue
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volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue
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status register. */
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volatile uint32_t resvd30;
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volatile uint32_t resvd34;
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@ -114,7 +114,7 @@ typedef struct {
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volatile uint32_t resvd58[48];
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volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size
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register. */
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volatile uint32_t DIEPTXF[15];/**< @brief Ddevice IN endpoint transmit FIFO
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volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO
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size registers. */
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volatile uint32_t resvd140[176];
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volatile uint32_t HCFG; /**< @brief Host configuration register. */
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@ -148,9 +148,9 @@ typedef struct {
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mask register. */
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volatile uint32_t resvd820;
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volatile uint32_t resvd824;
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volatile uint32_t DVBUSDIS; /**< @brief Device VBUS Discharge time
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volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time
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register. */
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volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS Pulsing time
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volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time
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register. */
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volatile uint32_t resvd830;
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volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty
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@ -387,130 +387,82 @@ typedef struct {
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/** @} */
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/**
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* @name GNPTXFSIZ register bit definitions
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* @name GCCFG register bit definitions
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* @{
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*/
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#define GNPTXFSIZ_NPTXFD_MASK (0xFFFFU<<16)/**< Non-periodic TxFIFO depth
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mask. */
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#define GNPTXFSIZ_NPTXFD(n) ((n##U)<<16)/**< Non-periodic TxFIFO depth
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value. */
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#define GNPTXFSIZ_NPTXFSA_MASK (0xFFFFU<<0)/**< Non-periodic transmit RAM
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start address mask. */
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#define GNPTXFSIZ_NPTXFSA(n) ((n##U)<<0) /**< Non-periodic transmit RAM
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start address value. */
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/** @} */
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/**
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* @name GNPTXSTS register bit definitions
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* @{
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*/
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#define GNPTXSTS_NPTxQTop_MASK (0x7F<<24) /**< Top of the non-periodic
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transmit request queue
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mask. */
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#define GNPTXSTS_NPTxQTop(n) ((n)<<24) /**< Top of the non-periodic
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transmit request queue
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value. */
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#define GNPTXSTS_NPTxQSpcAvail_MASK (0xFF<<16) /**< non-periodic transmit
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request queue Space
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Available mask. */
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#define GNPTXSTS_NPTxQSpcAvail(n) ((n)<<16) /**< non-periodic transmit
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request queue Space
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Available value. */
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#define GNPTXSTS_NPTxFSpcAvail_MASK (0xFFFF<<0) /**< non-periodic TxFIFO
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Space Available mask. */
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#define GNPTXSTS_NPTxFSpcAvail(n) ((n)<<0) /**< non-periodic TxFIFO
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Space Available value. */
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#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */
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#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B"
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device. */
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#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A"
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device. */
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#define GCCFG_PWRDWN (1U<<16) /**< Power down. */
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/** @} */
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/**
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* @name HPTXFSIZ register bit definitions
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* @{
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*/
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#define HPTXFSIZ_PTxFsize_MASK (0xFFFF<<16)/**< Host periodic TxFIFO
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Depth mask. */
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#define HPTXFSIZ_PTxFsize(n) ((n)<<16) /**< Host periodic TxFIFO
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Depth value. */
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#define HPTXFSIZ_PTxFStAddr_MASK (0xFFFF<<0) /**< Host periodic TxFIFO
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Start Address mask. */
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#define HPTXFSIZ_PTxFStAddr(n) ((n)<<0) /**< Host periodic TxFIFO
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Start Address value. */
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/** @} */
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/**
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* @name DPTXFSIZ register bit definitions
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* @{
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*/
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#define DPTXFSIZ_DPTxFsize_MASK (0xFFFF<<16 /**< Device periodic TxFIFO
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size mask. */
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#define DPTXFSIZ_DPTxFsize(n) ((n)<<16) /**< Device periodic TxFIFO
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size value. */
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#define DPTXFSIZ_DPTxFStAddr_MASK (0xFFFF<<0) /**< Device periodic TxFIFO
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RAM Start Address mask.*/
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#define DPTXFSIZ_DPTxFStAddr(n) ((n)<<0) /**< Device periodic TxFIFO
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RAM Start Address
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value. */
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#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO
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depth mask. */
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#define HPTXFSIZ_PTXFD(n) ((n##U)<<16)/**< Host periodic TxFIFO
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depth value. */
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#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO
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Start address mask. */
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#define HPTXFSIZ_PTXSA(n) ((n##U)<<0) /**< Host periodic TxFIFO
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start address value. */
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/** @} */
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/**
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* @name HCFG register bit definitions
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* @{
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*/
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#define HCFG_ResValid_MASK (0xFF<<8) /**< Resume Validation
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Period mask. */
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#define HCFG_ResValid(n) ((n)<<8) /**< Resume Validation
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Period value. */
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#define HCFG_Ena32KHzS (1U<<7) /**< enable 32-KHz suspend
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Mode. */
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#define HCFG_FSLSSupp (1U<<2) /**< FS- and LS-Only
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Support. */
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#define HCFG_FSLSPclkSel_MASK (3<<0) /**< FS/LS PHY clock Select
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#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */
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#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select
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mask. */
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#define HCFG_FSLSPclkSel_30_60 (0<<0) /**< PHY clock is running at
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30/60 MHz. */
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#define HCFG_FSLSPclkSel_48 (1U<<0) /**< PHY clock is running at
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#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at
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48 MHz. */
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#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at
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6 MHz. */
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/** @} */
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/**
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* @name HFIR register bit definitions
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* @{
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*/
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#define HFIR_FrInt_MASK (0xFFFF<<0) /**< frame interval mask. */
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#define HFIR_FrInt(n) ((n)<<0) /**< frame interval value. */
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#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */
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#define HFIR_FRIVL(n) ((n##U)<<0) /**< Frame interval value. */
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/** @} */
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/**
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* @name HFNUM register bit definitions
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* @{
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*/
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#define HFNUM_FrRem_MASK (0xFFFF<<16)/**< frame time Remaining
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mask. */
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#define HFNUM_FrRem(n) ((n)<<16) /**< frame time Remaining
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value. */
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#define HFNUM_FrNum_MASK (0xFFFF<<0) /**< frame number mask. */
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#define HFNUM_FrNum(n) ((n)<<0) /**< frame number value. */
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#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/
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#define HFNUM_FTREM(n) ((n##U)<<16)/**< Frame time Remaining value.*/
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#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */
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#define HFNUM_FRNUM(n) ((n##U)<<0) /**< Frame number value. */
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/** @} */
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/**
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* @name HPTXSTS register bit definitions
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* @{
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*/
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#define HPTXSTS_PTxQTop_MASK (0xFF<<24) /**< Top of the periodic
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#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic
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transmit request queue
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mask. */
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#define HPTXSTS_PTxQTop(n) ((n)<<24) /**< Top of the periodic
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#define HPTXSTS_PTXQTOP(n) ((n##U)<<24)/**< Top of the periodic
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transmit request queue
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value. */
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#define HPTXSTS_PTxQSpcAvail_MASK (0xFF<<16) /**< periodic transmit request
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#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request
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queue Space Available
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mask. */
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#define HPTXSTS_PTxQSpcAvail(n) ((n)<<16) /**< periodic transmit request
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#define HPTXSTS_PTXQSAV(n) ((n##U)<<16)/**< Periodic transmit request
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queue Space Available
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value. */
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#define HPTXSTS_PTxFSpcAvail_MASK (0xFFFF<<0) /**< periodic transmit Data
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#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data
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FIFO Space Available
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mask. */
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#define HPTXSTS_PTxFSpcAvail(n) ((n)<<0) /**< periodic transmit Data
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#define HPTXSTS_PTXFSAVL(n) ((n##U)<<0) /**< Periodic transmit Data
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FIFO Space Available
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value. */
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/** @} */
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@ -519,19 +471,17 @@ typedef struct {
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* @name HAINT register bit definitions
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* @{
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*/
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#define HAINT_HAINT_MASK (0xFFFF<<0) /**< channel interrupts
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mask. */
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#define HAINT_HAINT(n) ((n)<<0) /**< channel interrupts
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value. */
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#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */
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#define HAINT_HAINT(n) ((n##U)<<0) /**< Channel interrupts value. */
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/** @} */
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/**
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* @name HAINTMSK register bit definitions
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* @{
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*/
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#define HAINTMSK_HAINTMsk_MASK (0xFFFF<<0) /**< channel interrupt mask
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#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask
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mask. */
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#define HAINTMSK_HAINTMsk(n) ((n)<<0) /**< channel interrupt mask
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#define HAINTMSK_HAINTM(n) ((n##U)<<0) /**< Channel interrupt mask
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value. */
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/** @} */
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@ -539,134 +489,104 @@ typedef struct {
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* @name HPRT register bit definitions
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* @{
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*/
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#define HPRT_PrtSpd_MASK (3<<17) /**< port Speed mask. */
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#define HPRT_PrtSpd_HS (0<<17) /**< High Speed value. */
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#define HPRT_PrtSpd_FS (1U<<17) /**< Full Speed value. */
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#define HPRT_PrtSpd_LS (2<<17) /**< Low Speed value. */
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#define HPRT_PrtTstCtl_MASK (15<<13) /**< port Test control mask.*/
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#define HPRT_PrtTstCtl(n) ((n)<<13) /**< port Test control
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value. */
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#define HPRT_PrtPwr (1U<<12) /**< port power. */
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#define HPRT_PrtLnSts_MASK (3<<11) /**< port Line status mask. */
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#define HPRT_PrtLnSts_DM (1U<<11) /**< Logic level of D-. */
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#define HPRT_PrtLnSts_DP (1U<<10) /**< Logic level of D+. */
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#define HPRT_PrtRst (1U<<8) /**< port reset. */
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#define HPRT_PrtSusp (1U<<7) /**< port suspend. */
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#define HPRT_PrtRes (1U<<6) /**< port Resume. */
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#define HPRT_PrtOvrCurrChng (1U<<5) /**< port Overcurrent
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change. */
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#define HPRT_PrtOvrCurrAct (1U<<4) /**< port Overcurrent
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Active. */
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#define HPRT_PrtEnChng (1U<<3) /**< port enable/Disable
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change. */
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#define HPRT_PrtEna (1U<<2) /**< port enable. */
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#define HPRT_PrtConnDet (1U<<1) /**< port Connect detected. */
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#define HPRT_PrtConnSts (1U<<0) /**< .*/
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#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */
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#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */
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#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */
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#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */
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#define HPRT_PTCTL(n) ((n##U)<<13)/**< Port Test control value. */
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#define HPRT_PPWR (1U<<12) /**< Port power. */
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#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */
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#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */
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#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */
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#define HPRT_PRST (1U<<8) /**< Port reset. */
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#define HPRT_PSUSP (1U<<7) /**< Port suspend. */
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#define HPRT_PRES (1U<<6) /**< Port Resume. */
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#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */
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#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */
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#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/
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#define HPRT_PENA (1U<<2) /**< Port enable. */
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#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */
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#define HPRT_PCSTS (1U<<0) /**< Port connect status. */
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/** @} */
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/**
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* @name HCCHAR register bit definitions
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* @{
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*/
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#define HCCHAR_ChEna (1u<<31) /**< channel enable. */
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#define HCCHAR_ChDis (1U<<30) /**< channel Disable. */
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#define HCCHAR_OddFrm (1U<<29) /**< Odd frame. */
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#define HCCHAR_DevAddr_MASK (0x7F<<22) /**< Device Address mask. */
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#define HCCHAR_DevAddr(n) ((n)<<22) /**< Device Address value. */
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#define HCCHAR_MC_EC_MASK (3<<20) /**< Multi count (MC) / Error
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count mask. */
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#define HCCHAR_MC_EC(n) ((n)<<20) /**< Multi count (MC) / Error
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count value. */
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#define HCCHAR_EPType_MASK (3<<18) /**< .*/
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#define HCCHAR_EPType(n) ((n)<<18) /**< endpoint Type mask. */
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#define HCCHAR_EPType_control (0<<18) /**< control endpoint value.*/
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#define HCCHAR_EPType_isochronous (1U<<18) /**< isochronous endpoint
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value. */
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#define HCCHAR_EPType_Bulk (2<<18) /**< Bulk endpoint value. */
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#define HCCHAR_EPType_interrupt (3<<18) /**< interrupt endpoint
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value. */
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#define HCCHAR_LSpdDev (1U<<17) /**< Low-Speed Device. */
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#define HCCHAR_EPDir (1U<<15) /**< endpoint Direction. */
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#define HCCHAR_EPNum_MASK (15<<11) /**< endpoint number mask. */
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#define HCCHAR_EPNum(n) ((n)<<11) /**< endpoint number value. */
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#define HCCHAR_MPS_MASK (11<<0) /**< Maximum Packet size
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mask. */
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#define HCCHAR_MPS(n) (11<<0) /**< Maximum Packet size
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value. */
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/** @} */
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/**
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* @name HCSPLT register bit definitions
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* @{
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*/
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#define HCSPLT_SpltEna (1u<<31) /**< Split enable. */
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#define HCSPLT_CompSplt (1U<<16) /**< Do Complete Split. */
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#define HCSPLT_XactPos_MASK (3<<14) /**< Transaction Position. */
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#define HCSPLT_XactPos_Mid (0<<14) /**< Middle. */
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#define HCSPLT_XactPos_end (1U<<14) /**< End. */
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#define HCSPLT_XactPos_Begin (2<<14) /**< Begin. */
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#define HCSPLT_XactPos_all (3<<14) /**< All. */
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#define HCSPLT_HubAddr_MASK (0x7F<<6) /**< Hub Address mask. */
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#define HCSPLT_HubAddr(n) ((n)<<n) /**< Hub Address value. */
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#define HCSPLT_PrtAddr_MASK (0x7F<<0) /**< port Address mask. */
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#define HCSPLT_PrtAddr(n) ((n)<<0) /**< port Address value. */
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#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */
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#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */
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#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */
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#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */
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#define HCCHAR_DAD(n) ((n##U)<<22)/**< Device Address value. */
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#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */
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#define HCCHAR_MCNT(n) ((n##U)<<20)/**< Multicount value. */
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#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
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#define HCCHAR_EPTYP(n) ((n##U)<<18)/**< Endpoint type value. */
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#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */
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#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/
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#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */
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#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */
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#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */
|
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#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */
|
||||
#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */
|
||||
#define HCCHAR_EPNUM(n) ((n##U)<<11)/**< Endpoint number value. */
|
||||
#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */
|
||||
#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name HCINT register bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define HCINT_DataTglErr (1U<<10) /**< Data Toggle Error. */
|
||||
#define HCINT_FrmOvrun (1U<<9) /**< frame Overrun. */
|
||||
#define HCINT_BblErr (1U<<8) /**< Babble Error. */
|
||||
#define HCINT_XactErr (1U<<7) /**< Transaction Error. */
|
||||
#define HCINT_NYET (1U<<6) /**< NYET Response Received
|
||||
#define HCINT_DTERR (1U<<10) /**< Data toggle error. */
|
||||
#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */
|
||||
#define HCINT_BBERR (1U<<8) /**< Babble error. */
|
||||
#define HCINT_TRERR (1U<<7) /**< Transaction Error. */
|
||||
#define HCINT_ACK (1U<<5) /**< ACK response
|
||||
received/transmitted
|
||||
interrupt. */
|
||||
#define HCINT_ACK (1U<<5) /**< ACK Response
|
||||
Received/transmitted
|
||||
#define HCINT_NAK (1U<<4) /**< NAK response received
|
||||
interrupt. */
|
||||
#define HCINT_NAK (1U<<4) /**< NAK Response Received
|
||||
#define HCINT_STALL (1U<<3) /**< STALL response received
|
||||
interrupt. */
|
||||
#define HCINT_STALL (1U<<3) /**< STALL Response Received
|
||||
interrupt. */
|
||||
#define HCINT_ChHltd (1U<<1) /**< channel Halted. */
|
||||
#define HCINT_XferCompl (1U<<0) /**< transfer completed. */
|
||||
#define HCINT_CHH (1U<<1) /**< Channel halted. */
|
||||
#define HCINT_XFRC (1U<<0) /**< Transfer completed. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name HCINTMSK register bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define HCINTMSK_DataTglErrMsk (1U<<10) /**< Data Toggle Error mask.*/
|
||||
#define HCINTMSK_FrmOvrunMsk (1U<<9) /**< frame Overrun mask. */
|
||||
#define HCINTMSK_BblErrMsk (1U<<8) /**< Babble Error mask. */
|
||||
#define HCINTMSK_XactErrMsk (1U<<7) /**< Transaction Error mask.*/
|
||||
#define HCINTMSK_NyetMsk (1U<<6) /**< NYET Response Received
|
||||
#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */
|
||||
#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */
|
||||
#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */
|
||||
#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */
|
||||
#define HCINTMSK_NYET (1U<<6) /**< NYET response received
|
||||
interrupt mask. */
|
||||
#define HCINTMSK_AckMsk (1U<<5) /**< ACK Response
|
||||
Received/transmitted
|
||||
#define HCINTMSK_ACKM (1U<<5) /**< ACK Response
|
||||
received/transmitted
|
||||
interrupt mask. */
|
||||
#define HCINTMSK_NakMsk (1U<<4) /**< NAK Response Received
|
||||
#define HCINTMSK_NAKM (1U<<4) /**< NAK response received
|
||||
interrupt mask. */
|
||||
#define HCINTMSK_StallMsk (1U<<3) /**< STALL Response Received
|
||||
#define HCINTMSK_STALLM (1U<<3) /**< STALL response received
|
||||
interrupt mask. */
|
||||
#define HCINTMSK_ChHltdMsk (1U<<1) /**< channel Halted mask. */
|
||||
#define HCINTMSK_XferComplMsk (1U<<0) /**< transfer completed
|
||||
mask.*/
|
||||
#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */
|
||||
#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name HCTSIZ register bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define HCTSIZ_DoPng (1U<<31) /**< Do Ping. */
|
||||
#define HCTSIZ_Pid_MASK (3<<29) /**< PID mask. */
|
||||
#define HCTSIZ_Pid_DATA0 (0<<29) /**< DATA0. */
|
||||
#define HCTSIZ_Pid_DATA2 (1U<<29) /**< DATA2. */
|
||||
#define HCTSIZ_Pid_DATA1 (2<<29) /**< DATA1. */
|
||||
#define HCTSIZ_Pid_MDATA (3<<29) /**< MDATA. */
|
||||
#define HCTSIZ_Xfersize_MASK (0x7FFFF<<0)/**< transfer size mask. */
|
||||
#define HCTSIZ_Xfersize(n) ((n)<<0) /**< transfer size value. */
|
||||
#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */
|
||||
#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */
|
||||
#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */
|
||||
#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */
|
||||
#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */
|
||||
#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
|
||||
#define HCTSIZ_PKTCNT(n) ((n##U)<<19)/**< Packet count value. */
|
||||
#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */
|
||||
#define HCTSIZ_XFRSIZ(n) ((n##U)<<0) /**< Transfer size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -675,18 +595,18 @@ typedef struct {
|
|||
*/
|
||||
#define DCFG_ResValid_MASK (0x3F<<26) /**< Resume Validation Period
|
||||
mask. */
|
||||
#define DCFG_ResValid(n) ((n)<<26) /**< Resume Validation Period
|
||||
#define DCFG_ResValid(n) ((n##U)<<26) /**< Resume Validation Period
|
||||
value. */
|
||||
#define DCFG_EPMiscnt_MASK (0x1F<<18) /**< IN endpoint Mismatch
|
||||
count mask. */
|
||||
#define DCFG_EPMiscnt(n) ((n)<<18) /**< IN endpoint Mismatch
|
||||
#define DCFG_EPMiscnt(n) ((n##U)<<18) /**< IN endpoint Mismatch
|
||||
count value. */
|
||||
#define DCFG_PerFrInt_MASK (3<<11) /**< periodic frame interval
|
||||
mask. */
|
||||
#define DCFG_PerFrInt(n) ((n)<<11) /**< periodic frame interval
|
||||
#define DCFG_PerFrInt(n) ((n##U)<<11) /**< periodic frame interval
|
||||
value. */
|
||||
#define DCFG_DevAddr_MASK (0x7F<<4) /**< Device Address mask. */
|
||||
#define DCFG_DevAddr(n) ((n)<<4) /**< Device Address value. */
|
||||
#define DCFG_DevAddr(n) ((n##U)<<4) /**< Device Address value. */
|
||||
#define DCFG_Ena32KHzS (1U<<3) /**< enable 32-KHz suspend
|
||||
Mode. */
|
||||
#define DCFG_NZStsOUTHShk (1U<<2) /**< non-Zero-Length status
|
||||
|
|
@ -719,7 +639,7 @@ typedef struct {
|
|||
#define DCTL_SGNPInNak (1U<<7) /**< Set Global non-periodic
|
||||
IN NAK. */
|
||||
#define DCTL_TstCtl_MASK (7<<4) /**< Test control mask. */
|
||||
#define DCTL_TstCtl(n) ((n)<<4) /**< Test control value. */
|
||||
#define DCTL_TstCtl(n) ((n##U)<<4) /**< Test control value. */
|
||||
#define DCTL_GOUTNakSts (1U<<3) /**< Global OUT NAK status. */
|
||||
#define DCTL_GNPINNakSts (1U<<2) /**< Global non-periodic IN
|
||||
NAK status. */
|
||||
|
|
@ -735,7 +655,7 @@ typedef struct {
|
|||
#define DSTS_SOFFN_MASK (0x3FFF<<8) /**< frame or Microframe
|
||||
number of the Received
|
||||
SOF mask. */
|
||||
#define DSTS_SOFFN(n) ((n)<<8) /**< frame or Microframe
|
||||
#define DSTS_SOFFN(n) ((n##U)<<8) /**< frame or Microframe
|
||||
number of the Received
|
||||
SOF value. */
|
||||
#define DSTS_ErrticErr (1U<<3) /**< Erratic Error. */
|
||||
|
|
@ -803,11 +723,11 @@ typedef struct {
|
|||
*/
|
||||
#define DAINT_OutEPInt_MASK (0xFFFF<<16)/**< OUT endpoint interrupt
|
||||
Bits mask. */
|
||||
#define DAINT_OutEPInt(n) ((n)<<16) /**< OUT endpoint interrupt
|
||||
#define DAINT_OutEPInt(n) ((n##U)<<16) /**< OUT endpoint interrupt
|
||||
Bits value. */
|
||||
#define DAINT_InEpInt_MASK (0xFFFF<<0) /**< IN endpoint interrupt
|
||||
Bits mask. */
|
||||
#define DAINT_InEpInt(n) ((n)<<0) /**< IN endpoint interrupt
|
||||
#define DAINT_InEpInt(n) ((n##U)<<0) /**< IN endpoint interrupt
|
||||
Bits value. */
|
||||
/** @} */
|
||||
|
||||
|
|
@ -831,7 +751,7 @@ typedef struct {
|
|||
*/
|
||||
#define DVBUSDIS_DVBUSDis_MASK (0xFFFF<<0) /**< Device VBUS Discharge
|
||||
time mask. */
|
||||
#define DVBUSDIS_DVBUSDis(n) ((n)<<0) /**< Device VBUS Discharge
|
||||
#define DVBUSDIS_DVBUSDis(n) ((n##U)<<0) /**< Device VBUS Discharge
|
||||
time value. */
|
||||
/** @} */
|
||||
|
||||
|
|
@ -841,7 +761,7 @@ typedef struct {
|
|||
*/
|
||||
#define DVBUSPULSE_DVBUSPulse_MASK (0xFFF<<0) /**< Device VBUS Pulsing time
|
||||
mask. */
|
||||
#define DVBUSPULSE_DVBUSPulse(n) ((n)<<0) /**< Device VBUS Pulsing time
|
||||
#define DVBUSPULSE_DVBUSPulse(n) ((n##U)<<0) /**< Device VBUS Pulsing time
|
||||
value. */
|
||||
/** @} */
|
||||
|
||||
|
|
@ -856,7 +776,7 @@ typedef struct {
|
|||
#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
|
||||
#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
|
||||
#define DIEPCTL_TxFNum_MASK (15<<22) /**< TxFIFO number mask. */
|
||||
#define DIEPCTL_TxFNum(n) ((n)<<22) /**< TxFIFO number value. */
|
||||
#define DIEPCTL_TxFNum(n) ((n##U)<<22) /**< TxFIFO number value. */
|
||||
#define DIEPCTL_Stall (1U<<21) /**< STALL Handshake. */
|
||||
#define DIEPCTL_Snp (1U<<20) /**< Snoop Mode. */
|
||||
#define DIEPCTL_EPType_MASK (3<<18) /**< endpoint Type mask. */
|
||||
|
|
@ -868,10 +788,10 @@ typedef struct {
|
|||
#define DIEPCTL_DPID (1U<<16) /**< endpoint Data PID. */
|
||||
#define DIEPCTL_USBActEP (1U<<15) /**< USB Active endpoint. */
|
||||
#define DIEPCTL_NextEp_MASK (15<<11) /**< Next endpoint mask. */
|
||||
#define DIEPCTL_NextEp(n) ((n)<<11) /**< Next endpoint value. */
|
||||
#define DIEPCTL_NextEp(n) ((n##U)<<11) /**< Next endpoint value. */
|
||||
#define DIEPCTL_MPS_MASK (0x3FF<<0) /**< Maximum Packet size
|
||||
mask. */
|
||||
#define DIEPCTL_MPS(n) ((n)<<0) /**< Maximum Packet size
|
||||
#define DIEPCTL_MPS(n) ((n##U)<<0) /**< Maximum Packet size
|
||||
value. */
|
||||
/** @} */
|
||||
|
||||
|
|
@ -902,11 +822,11 @@ typedef struct {
|
|||
* @{
|
||||
*/
|
||||
#define DIEPTSIZ_MC_MASK (3<<29) /**< Multi count mask. */
|
||||
#define DIEPTSIZ_MC(n) ((n)<<29) /**< Multi count value. */
|
||||
#define DIEPTSIZ_MC(n) ((n##U)<<29) /**< Multi count value. */
|
||||
#define DIEPTSIZ_Pktcnt_MASK (0x3FF<<19) /**< Packet count mask. */
|
||||
#define DIEPTSIZ_Pktcnt(n) ((n)<<19) /**< Packet count value. */
|
||||
#define DIEPTSIZ_Pktcnt(n) ((n##U)<<19) /**< Packet count value. */
|
||||
#define DIEPTSIZ_Xfersize_MASK (0x7FFFF<<0)/**< transfer size mask. */
|
||||
#define DIEPTSIZ_Xfersize(n) ((n)<<0) /**< transfer size value. */
|
||||
#define DIEPTSIZ_Xfersize(n) ((n##U)<<0) /**< transfer size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -930,10 +850,10 @@ typedef struct {
|
|||
#define DOEPCTL_EO_FrNum (1U<<16) /**< Even/Odd (Micro)frame. */
|
||||
#define DOEPCTL_USBActEP (1U<<15) /**< USB Active endpoint. */
|
||||
#define DOEPCTL_NextEp_MASK (15<<11) /**< Next endpoint mask. */
|
||||
#define DOEPCTL_NextEp(n) ((n)<<11) /**< Next endpoint value. */
|
||||
#define DOEPCTL_NextEp(n) ((n##U)<<11) /**< Next endpoint value. */
|
||||
#define DOEPCTL_MPS_MASK (0x3FF<<0) /**< Maximum Packet size
|
||||
mask. */
|
||||
#define DOEPCTL_MPS(n) ((n)<<0) /**< Maximum Packet size
|
||||
#define DOEPCTL_MPS(n) ((n##U)<<0) /**< Maximum Packet size
|
||||
value. */
|
||||
/** @} */
|
||||
|
||||
|
|
@ -962,11 +882,11 @@ typedef struct {
|
|||
* @{
|
||||
*/
|
||||
#define DOEPTSIZ_SUPcnt_MASK (3<<29) /**< SETUP Packet cnt mask. */
|
||||
#define DOEPTSIZ_SUPcnt(n) ((n)<<29) /**< SETUP Packet cnt value.*/
|
||||
#define DOEPTSIZ_SUPcnt(n) ((n##U)<<29) /**< SETUP Packet cnt value.*/
|
||||
#define DOEPTSIZ_Pktcnt_MASK (0x3FF<<19) /**< Packet count mask. */
|
||||
#define DOEPTSIZ_Pktcnt(n) ((n)<<19) /**< Packet count value. */
|
||||
#define DOEPTSIZ_Pktcnt(n) ((n##U)<<19) /**< Packet count value. */
|
||||
#define DOEPTSIZ_Xfersize_MASK (0x7FFFF<<0)/**< transfer size mask. */
|
||||
#define DOEPTSIZ_Xfersize(n) ((n)<<0) /**< transfer size value. */
|
||||
#define DOEPTSIZ_Xfersize(n) ((n##U)<<0) /**< transfer size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue