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STM32L4+ preliminary work. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11874 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-04-04 11:58:19 +00:00
parent cad3247673
commit 81e08e2394
26 changed files with 386504 additions and 387564 deletions
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2
os/common/ext/ST/STM32L4xx/stm32l431xx.h
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@ -776,8 +776,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l432xx.h
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@ -743,8 +743,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l433xx.h
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@ -792,8 +792,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l442xx.h
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@ -744,8 +744,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l443xx.h
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@ -793,8 +793,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l451xx.h
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@ -815,8 +815,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l452xx.h
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@ -816,8 +816,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l462xx.h
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@ -817,8 +817,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l471xx.h
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@ -850,8 +850,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l475xx.h
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@ -851,8 +851,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l476xx.h
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@ -866,8 +866,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l485xx.h
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@ -852,8 +852,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

2
os/common/ext/ST/STM32L4xx/stm32l486xx.h
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@ -867,8 +867,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;

9
os/common/ext/ST/STM32L4xx/stm32l496xx.h
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@ -505,9 +505,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -938,8 +938,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;
@ -7777,7 +7775,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/

9
os/common/ext/ST/STM32L4xx/stm32l4a6xx.h
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@ -506,9 +506,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -939,8 +939,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
} SPI_TypeDef;
@ -8022,7 +8020,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/

465
os/common/ext/ST/STM32L4xx/stm32l4r5xx.h
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@ -176,8 +176,6 @@ typedef enum
I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
DCMI_IRQn = 85, /*!< DCMI global interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
LTDC_IRQn = 91, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */
DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
} IRQn_Type;
@ -352,9 +350,7 @@ typedef struct
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
@ -521,11 +517,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */
__IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -698,54 +692,6 @@ typedef struct
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
@ -845,8 +791,6 @@ typedef struct
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */
__IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
} OCTOSPI_TypeDef;
/**
@ -1023,8 +967,6 @@ typedef struct
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
@ -1039,8 +981,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */
__IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */
} SPI_TypeDef;
@ -1140,8 +1080,6 @@ typedef struct
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
} USART_TypeDef;
/**
@ -1390,9 +1328,6 @@ typedef struct
#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
@ -1569,9 +1504,6 @@ typedef struct
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
@ -6206,8 +6138,8 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
@ -7976,15 +7908,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_VERR register *****************/
#define DMA2D_VERR_MINREV_Pos (0U)
#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define DMA2D_VERR_MAJREV_Pos (4U)
#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
@ -10601,289 +10524,6 @@ typedef struct
#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE_Pos (1U)
#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF_Pos (1U)
#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF_Pos (1U)
#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
#define LTDC_LxCR_COLKEN_Pos (1U)
#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
@ -12704,9 +12344,6 @@ typedef struct
#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
#define RCC_APB2RSTR_LTDCRST_Pos (26U)
#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
@ -12908,9 +12545,6 @@ typedef struct
#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
#define RCC_APB2ENR_LTDCEN_Pos (26U)
#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
@ -13118,9 +12752,6 @@ typedef struct
#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
#define RCC_APB2SMENR_LTDCSMEN_Pos (26U)
#define RCC_APB2SMENR_LTDCSMEN_Msk (0x1U << RCC_APB2SMENR_LTDCSMEN_Pos) /*!< 0x04000000 */
#define RCC_APB2SMENR_LTDCSMEN RCC_APB2SMENR_LTDCSMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
@ -13372,9 +13003,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -14728,12 +14356,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -14891,13 +14519,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -14920,14 +14562,6 @@ typedef struct
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/****************** Bit definition for SDMMC_VERR register ********************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@ -15083,14 +14717,6 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_VERR register ********************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPI */
@ -15421,14 +15047,6 @@ typedef struct
#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/****************** Bit definition for OCTOSPI_VERR register *****************/
#define OCTOSPI_VERR_MINREV_Pos (0U)
#define OCTOSPI_VERR_MINREV_Msk (0xFU << OCTOSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define OCTOSPI_VERR_MINREV OCTOSPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define OCTOSPI_VERR_MAJREV_Pos (4U)
#define OCTOSPI_VERR_MAJREV_Msk 0xFU << OCTOSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define OCTOSPI_VERR_MAJREV OCTOSPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPIM */
@ -17080,12 +16698,6 @@ typedef struct
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
@ -18344,14 +17956,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************* Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* VREFBUF */
@ -19995,9 +19599,6 @@ typedef struct
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
/******************************* HCD Instances *******************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

126
os/common/ext/ST/STM32L4xx/stm32l4r7xx.h
View File

@ -353,9 +353,7 @@ typedef struct
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
@ -522,11 +520,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */
__IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -647,9 +643,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1009]; /*!< Reserved2, Address offset: 0x30 to 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0xFF8 to 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -869,8 +863,6 @@ typedef struct
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */
__IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
} OCTOSPI_TypeDef;
/**
@ -1047,8 +1039,6 @@ typedef struct
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
@ -1063,8 +1053,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */
__IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */
} SPI_TypeDef;
@ -1164,8 +1152,6 @@ typedef struct
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
} USART_TypeDef;
/**
@ -6238,8 +6224,8 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
@ -8008,15 +7994,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_VERR register *****************/
#define DMA2D_VERR_MINREV_Pos (0U)
#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define DMA2D_VERR_MAJREV_Pos (4U)
#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
@ -9341,14 +9318,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFU << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFU << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFU << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1U << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -13533,9 +13502,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -14889,12 +14855,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -15052,13 +15018,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -15081,14 +15061,6 @@ typedef struct
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/****************** Bit definition for SDMMC_VERR register ********************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@ -15244,14 +15216,6 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_VERR register ********************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPI */
@ -15582,14 +15546,6 @@ typedef struct
#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/****************** Bit definition for OCTOSPI_VERR register *****************/
#define OCTOSPI_VERR_MINREV_Pos (0U)
#define OCTOSPI_VERR_MINREV_Msk (0xFU << OCTOSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define OCTOSPI_VERR_MINREV OCTOSPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define OCTOSPI_VERR_MAJREV_Pos (4U)
#define OCTOSPI_VERR_MAJREV_Msk 0xFU << OCTOSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define OCTOSPI_VERR_MAJREV OCTOSPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPIM */
@ -17241,12 +17197,6 @@ typedef struct
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
@ -18505,14 +18455,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************* Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* VREFBUF */

126
os/common/ext/ST/STM32L4xx/stm32l4r9xx.h
View File

@ -354,9 +354,7 @@ typedef struct
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
@ -523,11 +521,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */
__IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -727,9 +723,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1009]; /*!< Reserved2, Address offset: 0x30 to 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0xFF8 to 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -949,8 +943,6 @@ typedef struct
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */
__IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
} OCTOSPI_TypeDef;
/**
@ -1127,8 +1119,6 @@ typedef struct
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
@ -1143,8 +1133,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */
__IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */
} SPI_TypeDef;
@ -1244,8 +1232,6 @@ typedef struct
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
} USART_TypeDef;
/**
@ -6320,8 +6306,8 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
@ -8090,15 +8076,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_VERR register *****************/
#define DMA2D_VERR_MINREV_Pos (0U)
#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define DMA2D_VERR_MAJREV_Pos (4U)
#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
@ -12460,14 +12437,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFU << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFU << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFU << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1U << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -16665,9 +16634,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -18021,12 +17987,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -18184,13 +18150,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -18213,14 +18193,6 @@ typedef struct
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/****************** Bit definition for SDMMC_VERR register ********************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@ -18376,14 +18348,6 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_VERR register ********************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPI */
@ -18714,14 +18678,6 @@ typedef struct
#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/****************** Bit definition for OCTOSPI_VERR register *****************/
#define OCTOSPI_VERR_MINREV_Pos (0U)
#define OCTOSPI_VERR_MINREV_Msk (0xFU << OCTOSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define OCTOSPI_VERR_MINREV OCTOSPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define OCTOSPI_VERR_MAJREV_Pos (4U)
#define OCTOSPI_VERR_MAJREV_Msk 0xFU << OCTOSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define OCTOSPI_VERR_MAJREV OCTOSPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPIM */
@ -20373,12 +20329,6 @@ typedef struct
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
@ -21637,14 +21587,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************* Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* VREFBUF */

465
os/common/ext/ST/STM32L4xx/stm32l4s5xx.h
View File

@ -177,8 +177,6 @@ typedef enum
I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
DCMI_IRQn = 85, /*!< DCMI global interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
LTDC_IRQn = 91, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */
DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
} IRQn_Type;
@ -353,9 +351,7 @@ typedef struct
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
@ -522,11 +518,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */
__IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -699,54 +693,6 @@ typedef struct
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
@ -846,8 +792,6 @@ typedef struct
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */
__IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
} OCTOSPI_TypeDef;
/**
@ -1024,8 +968,6 @@ typedef struct
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
@ -1040,8 +982,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */
__IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */
} SPI_TypeDef;
@ -1141,8 +1081,6 @@ typedef struct
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
} USART_TypeDef;
/**
@ -1448,9 +1386,6 @@ typedef struct
#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
@ -1630,9 +1565,6 @@ typedef struct
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
@ -6270,8 +6202,8 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
@ -8228,15 +8160,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_VERR register *****************/
#define DMA2D_VERR_MINREV_Pos (0U)
#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define DMA2D_VERR_MAJREV_Pos (4U)
#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
@ -10930,289 +10853,6 @@ typedef struct
#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE_Pos (1U)
#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF_Pos (1U)
#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF_Pos (1U)
#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
#define LTDC_LxCR_COLKEN_Pos (1U)
#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0x0FFF0000 */
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
/******************************************************************************/
/* */
/* Power Control */
@ -13039,9 +12679,6 @@ typedef struct
#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
#define RCC_APB2RSTR_LTDCRST_Pos (26U)
#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
@ -13249,9 +12886,6 @@ typedef struct
#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
#define RCC_APB2ENR_LTDCEN_Pos (26U)
#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
@ -13465,9 +13099,6 @@ typedef struct
#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
#define RCC_APB2SMENR_LTDCSMEN_Pos (26U)
#define RCC_APB2SMENR_LTDCSMEN_Msk (0x1U << RCC_APB2SMENR_LTDCSMEN_Pos) /*!< 0x04000000 */
#define RCC_APB2SMENR_LTDCSMEN RCC_APB2SMENR_LTDCSMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
@ -13719,9 +13350,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -15075,12 +14703,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -15238,13 +14866,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -15267,14 +14909,6 @@ typedef struct
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/****************** Bit definition for SDMMC_VERR register ********************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@ -15430,14 +15064,6 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_VERR register ********************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPI */
@ -15768,14 +15394,6 @@ typedef struct
#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/****************** Bit definition for OCTOSPI_VERR register *****************/
#define OCTOSPI_VERR_MINREV_Pos (0U)
#define OCTOSPI_VERR_MINREV_Msk (0xFU << OCTOSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define OCTOSPI_VERR_MINREV OCTOSPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define OCTOSPI_VERR_MAJREV_Pos (4U)
#define OCTOSPI_VERR_MAJREV_Msk 0xFU << OCTOSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define OCTOSPI_VERR_MAJREV OCTOSPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPIM */
@ -17427,12 +17045,6 @@ typedef struct
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
@ -18691,14 +18303,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************* Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* VREFBUF */
@ -20345,9 +19949,6 @@ typedef struct
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
/******************************* HCD Instances *******************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

126
os/common/ext/ST/STM32L4xx/stm32l4s7xx.h
View File

@ -354,9 +354,7 @@ typedef struct
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
@ -523,11 +521,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */
__IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -648,9 +644,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1009]; /*!< Reserved2, Address offset: 0x30 to 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0xFF8 to 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -870,8 +864,6 @@ typedef struct
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */
__IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
} OCTOSPI_TypeDef;
/**
@ -1048,8 +1040,6 @@ typedef struct
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
@ -1064,8 +1054,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */
__IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */
} SPI_TypeDef;
@ -1165,8 +1153,6 @@ typedef struct
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
} USART_TypeDef;
/**
@ -6302,8 +6288,8 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
@ -8260,15 +8246,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_VERR register *****************/
#define DMA2D_VERR_MINREV_Pos (0U)
#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define DMA2D_VERR_MAJREV_Pos (4U)
#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
@ -9593,14 +9570,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFU << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFU << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFU << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1U << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -13880,9 +13849,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -15236,12 +15202,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -15399,13 +15365,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -15428,14 +15408,6 @@ typedef struct
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/****************** Bit definition for SDMMC_VERR register ********************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@ -15591,14 +15563,6 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_VERR register ********************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPI */
@ -15929,14 +15893,6 @@ typedef struct
#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/****************** Bit definition for OCTOSPI_VERR register *****************/
#define OCTOSPI_VERR_MINREV_Pos (0U)
#define OCTOSPI_VERR_MINREV_Msk (0xFU << OCTOSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define OCTOSPI_VERR_MINREV OCTOSPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define OCTOSPI_VERR_MAJREV_Pos (4U)
#define OCTOSPI_VERR_MAJREV_Msk 0xFU << OCTOSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define OCTOSPI_VERR_MAJREV OCTOSPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPIM */
@ -17588,12 +17544,6 @@ typedef struct
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
@ -18852,14 +18802,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************* Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* VREFBUF */

126
os/common/ext/ST/STM32L4xx/stm32l4s9xx.h
View File

@ -355,9 +355,7 @@ typedef struct
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
@ -524,11 +522,9 @@ typedef struct
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */
__IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
@ -728,9 +724,7 @@ typedef struct
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1009]; /*!< Reserved2, Address offset: 0x30 to 0xFF0 */
__IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0xFF8 to 0xFFC */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
@ -950,8 +944,6 @@ typedef struct
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */
__IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
} OCTOSPI_TypeDef;
/**
@ -1128,8 +1120,6 @@ typedef struct
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
@ -1144,8 +1134,6 @@ typedef struct
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */
__IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */
} SPI_TypeDef;
@ -1245,8 +1233,6 @@ typedef struct
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
} USART_TypeDef;
/**
@ -6384,8 +6370,8 @@ typedef struct
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
@ -8342,15 +8328,6 @@ typedef struct
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_VERR register *****************/
#define DMA2D_VERR_MINREV_Pos (0U)
#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define DMA2D_VERR_MAJREV_Pos (4U)
#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
@ -12712,14 +12689,6 @@ typedef struct
#define GFXMMU_B3CR_PBBA_Msk (0x1FFU << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_VERR register ******************/
#define GFXMMU_VERR_MINREV_Pos (0U)
#define GFXMMU_VERR_MINREV_Msk (0xFU << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define GFXMMU_VERR_MAJREV_Pos (4U)
#define GFXMMU_VERR_MAJREV_Msk (0xFU << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1U << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
@ -17012,9 +16981,6 @@ typedef struct
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_BYP_Pos (6U)
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
#define RNG_CR_BYP RNG_CR_BYP_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
@ -18368,12 +18334,12 @@ typedef struct
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@ -18531,13 +18497,27 @@ typedef struct
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
@ -18560,14 +18540,6 @@ typedef struct
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/****************** Bit definition for SDMMC_VERR register ********************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
@ -18723,14 +18695,6 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_VERR register ********************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPI */
@ -19061,14 +19025,6 @@ typedef struct
#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/****************** Bit definition for OCTOSPI_VERR register *****************/
#define OCTOSPI_VERR_MINREV_Pos (0U)
#define OCTOSPI_VERR_MINREV_Msk (0xFU << OCTOSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define OCTOSPI_VERR_MINREV OCTOSPI_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
#define OCTOSPI_VERR_MAJREV_Pos (4U)
#define OCTOSPI_VERR_MAJREV_Msk 0xFU << OCTOSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define OCTOSPI_VERR_MAJREV OCTOSPI_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* OCTOSPIM */
@ -20720,12 +20676,6 @@ typedef struct
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
@ -21984,14 +21934,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************* Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/******************************************************************************/
/* */
/* VREFBUF */

4
os/common/ext/ST/STM32L4xx/stm32l4xx.h
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@ -114,11 +114,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number $VERSION$
* @brief CMSIS Device version number
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\

15
os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h
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@ -48,7 +48,9 @@
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#if defined(STM32L496xx) || defined(STM32L4A6xx)
#if defined(STM32L496xx) || defined(STM32L4A6xx) || defined(STM32L4R5xx) || \
defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define CORTEX_NUM_VECTORS 96
#else
#define CORTEX_NUM_VECTORS 88
@ -61,10 +63,17 @@
/* If the device type is not externally defined, for example from the Makefile,
then a file named board.h is included. This file must contain a device
definition compatible with the vendor include file.*/
#if !defined(STM32L471xx) && !defined(STM32L475xx) && \
#if !defined(STM32L431xx) && !defined(STM32L432xx) && \
!defined(STM32L433xx) && !defined(STM32L442xx) && \
!defined(STM32L443xx) && !defined(STM32L451xx) && \
!defined(STM32L452xx) && !defined(STM32L462xx) && \
!defined(STM32L471xx) && !defined(STM32L475xx) && \
!defined(STM32L476xx) && !defined(STM32L485xx) && \
!defined(STM32L486xx) && !defined(STM32L496xx) && \
!defined(STM32L4A6xx)
!defined(STM32L4A6xx) && \
!defined(STM32L4R5xx) && !defined(STM32L4R7xx) && \
!defined(STM32L4R9xx) && !defined(STM32L4S5xx) && \
!defined(STM32L4S7xx) && !defined(STM32L4S9xx) && \
#include "board.h"
#endif

26
os/hal/ports/STM32/STM32L4xx/hal_lld.h
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@ -217,12 +217,6 @@
#define STM32_UART4SEL_HSI16 (2 << 6) /**< UART4 source is HSI16. */
#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
#define STM32_UART5SEL_HSI16 (2 << 8) /**< UART5 source is HSI16. */
#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */
#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */
#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */
@ -263,13 +257,6 @@
#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */
#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
#define STM32_SAI2SEL_MASK (3 << 24) /**< SAI2SEL mask. */
#define STM32_SAI2SEL_PLLSAI1 (0 << 24) /**< SAI2 source is PLLSAI1-P. */
#define STM32_SAI2SEL_PLLSAI2 (1 << 24) /**< SAI2 source is PLLSAI2-P. */
#define STM32_SAI2SEL_PLL (2 << 24) /**< SAI2 source is PLL-P. */
#define STM32_SAI2SEL_EXTCLK (3 << 24) /**< SAI2 source is external. */
#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
#if !STM32_CLOCK_HAS_HSI48
#define STM32_CLK48SEL_NOCLK (0 << 26) /**< CLK48 disabled. */
@ -283,16 +270,21 @@
#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */
#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */
#define STM32_ADCSEL_PLLSAI1 (1 << 28) /**< ADC source is PLLSAI1-R. */
#define STM32_ADCSEL_PLLSAI2 (2 << 28) /**< ADC source is PLLSAI2-R. */
#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */
#define STM32_SWPMI1SEL_MASK (1 << 30) /**< SWPMI1SEL mask. */
#define STM32_SWPMI1SEL_PCLK1 (0 << 30) /**< SWPMI1 source is PCLK1. */
#define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
/** @} */
#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
#define STM32_DFSDMSEL_PCLK1 (0 << 31) /**< DFSDM source is PCLK1. */
#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
/**
* @name RCC_CCIPR2 register bits definitions
* @{
*/
#define STM32_I2C4SEL_MASK (3 << 0) /**< I2C1SEL mask. */
#define STM32_I2C4SEL_PCLK1 (0 << 0) /**< I2C1 source is PCLK1. */
#define STM32_I2C4SEL_SYSCLK (1 << 0) /**< I2C1 source is SYSCLK. */
#define STM32_I2C4SEL_HSI16 (2 << 0) /**< I2C1 source is HSI16. */
/** @} */
/**

1
readme.txt
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@ -94,6 +94,7 @@
*****************************************************************************
*** Next ***
- NEW: Updated STM32L4xx headers to version 1.11.0.
- NEW: Added HAL support for STM32L443.
- NEW: Added support for LDM303AGR 6 axis Accelerometer\Magnetometer MEMS.
- NEW: Added support for LSM6DSL 6 axis Accelerometer\Gyroscope MEMS.