git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13008 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
a3743f4e53
commit
821e535522
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@ -85,6 +85,7 @@
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* @{
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*/
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#define STM32_HSI16CLK 16000000U /**< 16MHz internal clock. */
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#define STM32_HSI48CLK 48000000U /**< 48MHz internal clock. */
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#define STM32_LSICLK 32000U /**< Low speed internal clock. */
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/** @} */
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@ -149,8 +150,8 @@
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#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
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#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
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#define STM32_PPRE1_MASK (7U << 7U) /**< PPRE1 field mask. */
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#define STM32_PPRE1_FIELD(n) ((n) << 7U) /**< PPRE1 field value. */
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#define STM32_PPRE1_MASK (7U << 7U) /**< PPRE1 field mask. */
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#define STM32_PPRE1_FIELD(n) ((n) << 7U) /**< PPRE1 field value. */
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#define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U)
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#define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U)
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#define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U)
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@ -210,9 +211,23 @@
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#define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */
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#define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */
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#define STM32_CECSEL_MASK (1U << 6U) /**< CEC mask. */
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#define STM32_CECSEL_HSI16DIV (0U << 6U) /**< CEC source is HSI16/448. */
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#define STM32_CECSEL_LSE (1U << 6U) /**< CEC source is LSE. */
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#define STM32_USART3SEL_MASK (3U << 4U) /**< USART3 mask. */
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#define STM32_USART3SEL_PCLK (0U << 4U) /**< USART3 source is PCLK. */
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#define STM32_USART3SEL_SYSCLK (1U << 4U) /**< USART3 source is SYSCLK. */
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#define STM32_USART3SEL_HSI16 (2U << 4U) /**< USART3 source is HSI16. */
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#define STM32_USART3SEL_LSE (3U << 4U) /**< USART3 source is LSE. */
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#define STM32_UART4SEL_MASK (3U << 6U) /**< UART4 mask. */
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#define STM32_UART4SEL_PCLK (0U << 6U) /**< UART4 source is PCLK. */
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#define STM32_UART4SEL_SYSCLK (1U << 6U) /**< UART4 source is SYSCLK. */
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#define STM32_UART4SEL_HSI16 (2U << 6U) /**< UART4 source is HSI16. */
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#define STM32_UART4SEL_LSE (3U << 6U) /**< UART4 source is LSE. */
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#define STM32_UART5SEL_MASK (3U << 8U) /**< UART5 mask. */
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#define STM32_UART5SEL_PCLK (0U << 8U) /**< UART5 source is PCLK. */
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#define STM32_UART5SEL_SYSCLK (1U << 8U) /**< UART5 source is SYSCLK. */
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#define STM32_UART5SEL_HSI16 (2U << 8U) /**< UART5 source is HSI16. */
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#define STM32_UART5SEL_LSE (3U << 8U) /**< UART5 source is LSE. */
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#define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */
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#define STM32_LPUART1SEL_PCLK (0U << 10U) /**< LPUART1 source is PCLK. */
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@ -225,11 +240,15 @@
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#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
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#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
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#define STM32_I2S1SEL_MASK (3U << 14U) /**< I2S1SEL mask. */
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#define STM32_I2S1SEL_SYSCLK (0U << 14U) /**< I2S1 source is SYSCLK. */
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#define STM32_I2S1SEL_PLLPCLK (1U << 14U) /**< I2S1 source is PLLPCLK. */
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#define STM32_I2S1SEL_HSI16 (2U << 14U) /**< I2S1 source is HSI16. */
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#define STM32_I2S1SEL_CKIN (3U << 14U) /**< I2S1 source is CKIN. */
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#define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C2SEL mask. */
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#define STM32_I2C2SEL_PCLK (0U << 14U) /**< I2C2 source is PCLK. */
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#define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C2 source is SYSCLK. */
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#define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C2 source is HSI16. */
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#define STM32_I2C3SEL_MASK (3U << 16U) /**< I2C3SEL mask. */
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#define STM32_I2C3SEL_PCLK (0U << 16U) /**< I2C3 source is PCLK. */
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#define STM32_I2C3SEL_SYSCLK (1U << 16U) /**< I2C3 source is SYSCLK. */
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#define STM32_I2C3SEL_HSI16 (2U << 16U) /**< I2C3 source is HSI16. */
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#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
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#define STM32_LPTIM1SEL_PCLK (0U << 18U) /**< LPTIM1 source is PCLK. */
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@ -237,37 +256,50 @@
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#define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */
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#define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */
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#define STM32_LPTIM2SEL_MASK (3U << 20U) /**< LPTIM2SEL mask. */
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#define STM32_LPTIM2SEL_PCLK (0U << 20U) /**< LPTIM2 source is PCLK. */
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#define STM32_LPTIM2SEL_LSI (1U << 20U) /**< LPTIM2 source is LSI. */
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#define STM32_LPTIM2SEL_HSI16 (2U << 20U) /**< LPTIM2 source is HSI16. */
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#define STM32_LPTIM2SEL_LSE (3U << 20U) /**< LPTIM2 source is LSE. */
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#define STM32_SAI1SEL_MASK (3U << 20U) /**< SAI1SEL mask. */
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#define STM32_SAI1SEL_SYSCLK (0U << 20U) /**< SAI1 source is SYSCLK. */
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#define STM32_SAI1SEL_PLLQCLK (1U << 20U) /**< SAI1 source is PLLQCLK. */
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#define STM32_SAI1SEL_CKIN (2U << 20U) /**< SAI1 source is CKIN. */
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#define STM32_SAI1SEL_HSI16 (3U << 20U) /**< SAI1 source is HSI16. */
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#define STM32_TIM1SEL_MASK (1U << 22U) /**< TIM1SEL mask. */
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#define STM32_TIM1SEL_TIMPCLK (0U << 22U) /**< TIM1SEL source is TIMPCLK. */
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#define STM32_TIM1SEL_PLLQCLK (1U << 22U) /**< TIM1SEL source is PLLQCLK. */
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#define STM32_I2S23SEL_MASK (3U << 22U) /**< I2S23SEL mask. */
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#define STM32_I2S23SEL_SYSCLK (0U << 22U) /**< I2S23 source is SYSCLK. */
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#define STM32_I2S23SEL_PLLQCLK (1U << 22U) /**< I2S23 source is PLLQCLK. */
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#define STM32_I2S23SEL_CKIN (2U << 22U) /**< I2S23 source is CKIN. */
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#define STM32_I2S23SEL_HSI16 (3U << 22U) /**< I2S23 source is HSI16. */
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#define STM32_TIM15SEL_MASK (1U << 24U) /**< TIM15SEL mask. */
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#define STM32_TIM15SEL_TIMPCLK (0U << 24U) /**< TIM15SEL source is TIMPCLK.*/
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#define STM32_TIM15SEL_PLLQCLK (1U << 24U) /**< TIM15SEL source is PLLQCLK.*/
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#define STM32_FDCANSEL_MASK (3U << 24U) /**< FDCANSEL mask. */
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#define STM32_FDCANSEL_HSE (0U << 24U) /**< FDCAN source is HSE. */
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#define STM32_FDCANSEL_PLLQCLK (2U << 24U) /**< FDCAN source is PLLQCLK. */
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#define STM32_RNGSEL_MASK (3U << 26U) /**< RNGSEL mask. */
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#define STM32_RNGSEL_NOCLOCK (0U << 26U) /**< RNG source is disabled. */
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#define STM32_RNGSEL_HSI16 (1U << 26U) /**< RNG source is HSI16. */
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#define STM32_RNGSEL_SYSCLK (2U << 26U) /**< RNG source is SYSCLK. */
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#define STM32_RNGSEL_PLLQCLK (3U << 26U) /**< RNG source is PLLQCLK. */
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#define STM32_CLK48SEL_MASK (3U << 26U) /**< CLK48SEL mask. */
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#define STM32_CLK48SEL_HSI48 (0U << 26U) /**< CLK48 source is HSI48. */
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#define STM32_CLK48SEL_PLLQCLK (2U << 26U) /**< CLK48 source is PLLQCLK. */
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#define STM32_RNGDIV_MASK (3U << 28U) /**< RNGDIV field mask. */
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#define STM32_RNGDIV_FIELD(n) ((n) << 28U)/**< RNGDIV field value */
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#define STM32_RNGDIV_1 STM32_RNGDIV_FIELD(0U)
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#define STM32_RNGDIV_2 STM32_RNGDIV_FIELD(1U)
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#define STM32_RNGDIV_4 STM32_RNGDIV_FIELD(2U)
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#define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U)
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#define STM32_ADC12SEL_MASK (3U << 30U) /**< ADCSEL mask. */
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#define STM32_ADC12SEL_NOCLK (0U << 30U) /**< ADC source is none. */
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#define STM32_ADC12SEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */
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#define STM32_ADC12SEL_SYSCLK (2U << 30U) /**< ADC source is SYSCLK. */
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#define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */
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#define STM32_ADCSEL_NOCLK (0U << 30U) /**< ADC source is SYSCLK. */
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#define STM32_ADCSEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */
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#define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
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#define STM32_ADC34SEL_MASK (3U << 30U) /**< ADCSEL mask. */
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#define STM32_ADC34SEL_NOCLK (0U << 30U) /**< ADC source is none. */
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#define STM32_ADC34SEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */
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#define STM32_ADC34SEL_SYSCLK (2U << 30U) /**< ADC source is SYSCLK. */
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/** @} */
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/**
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* @name RCC_CCIPR2 register bits definitions
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* @{
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*/
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#define STM32_I2C4SEL_MASK (3U << 0U) /**< I2C4SEL mask. */
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#define STM32_I2C4SEL_PCLK (0U << 0U) /**< I2C4 source is PCLK. */
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#define STM32_I2C4SEL_SYSCLK (1U << 0U) /**< I2C4 source is SYSCLK. */
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#define STM32_I2C4SEL_HSI16 (2U << 0U) /**< I2C4 source is HSI16. */
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#define STM32_QSPISEL_MASK (3U << 20U) /**< QSPISEL mask. */
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#define STM32_QSPISEL_SYSCLK (0U << 20U) /**< QSPI source is SYSCLK. */
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#define STM32_QSPISEL_HSI16 (1U << 20U) /**< QSPI source is HSI16. */
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#define STM32_QSPISEL_PLLQCLK (2U << 20U) /**< QSPI source is PLLQCLK. */
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/** @} */
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/**
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@ -319,14 +351,6 @@
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STM32_PVDE_DISABLED)
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#endif
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/**
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* @brief HSI16 divider value.
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* @note The allowed values are 1, 2, 4, 8, 16, 32, 64, 128.
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*/
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#if !defined(STM32_HSIDIV_VALUE) || defined(__DOXYGEN__)
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#define STM32_HSIDIV_VALUE 1
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#endif
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/**
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* @brief Enables or disables the HSI16 clock source.
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*/
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@ -334,6 +358,13 @@
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#define STM32_HSI16_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the HSI48 clock source.
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*/
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#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSI48_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the HSE clock source.
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*/
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@ -359,7 +390,7 @@
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* @brief Main clock source selection.
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* @note If the selected clock source is not the PLL then the PLL is not
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* initialized and started.
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* @note The default value is calculated for a 64MHz system clock from
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* @note The default value is calculated for a 168MHz system clock from
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_SW) || defined(__DOXYGEN__)
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@ -370,7 +401,7 @@
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* @brief Clock source for the PLL.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 64MHz system clock from
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* @note The default value is calculated for a 168MHz system clock from
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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@ -379,8 +410,8 @@
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/**
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* @brief PLLM divider value.
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* @note The allowed values are 1..8.
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* @note The default value is calculated for a 64MHz system clock from
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* @note The allowed values are 1..16.
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* @note The default value is calculated for a 168MHz system clock from
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
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@ -389,8 +420,8 @@
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/**
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* @brief PLLN multiplier value.
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* @note The allowed values are 8..86.
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* @note The default value is calculated for a 64MHz system clock from
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* @note The allowed values are 8..127.
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* @note The default value is calculated for a 168MHz system clock from
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
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@ -399,7 +430,7 @@
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/**
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* @brief PLLP divider value.
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* @note The allowed values are 2..32.
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* @note The allowed values are 7, 17.
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*/
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#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLP_VALUE 4
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/**
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* @brief PLLQ divider value.
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* @note The allowed values are 2..8.
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* @note The allowed values are 2, 4, 6, 8.
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*/
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#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLQ_VALUE 4
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@ -415,8 +446,8 @@
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/**
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* @brief PLLR divider value.
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* @note The allowed values are 2..8.
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* @note The default value is calculated for a 64MHz system clock from
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* @note The allowed values are 2, 4, 6, 8.
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* @note The default value is calculated for a 168MHz system clock from
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
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@ -425,7 +456,7 @@
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/**
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* @brief AHB prescaler value.
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* @note The default value is calculated for a 64MHz system clock from
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* @note The default value is calculated for a 168MHz system clock from
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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#endif
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/**
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* @brief USART3 clock source.
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*/
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#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
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#endif
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/**
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* @brief UART4 clock source.
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*/
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#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
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#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
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#endif
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/**
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* @brief UART5 clock source.
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*/
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#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
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#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
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#endif
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/**
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* @brief LPUART1 clock source.
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*/
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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#endif
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/**
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* @brief CEC clock source.
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*/
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#if !defined(STM32_CECSEL) || defined(__DOXYGEN__)
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#define STM32_CECSEL STM32_CECSEL_HSI16DIV
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#endif
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/**
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* @brief I2C1 clock source.
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*/
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@ -496,10 +541,24 @@
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#endif
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/**
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* @brief I2S1 clock source.
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* @brief I2C2 clock source.
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*/
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#if !defined(STM32_I2S1SEL) || defined(__DOXYGEN__)
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
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#define STM32_I2C2SEL STM32_I2C2SEL_PCLK
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#endif
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/**
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* @brief I2C3 clock source.
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*/
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#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
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#define STM32_I2C3SEL STM32_I2C3SEL_PCLK
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#endif
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/**
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* @brief I2C4 clock source.
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*/
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#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK
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#endif
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/**
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@ -510,45 +569,52 @@
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#endif
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/**
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* @brief LPTIM2 clock source.
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* @brief SAI1 clock source.
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*/
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#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__)
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK
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#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
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#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
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#endif
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/**
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* @brief TIM1 clock source.
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* @brief I2S23 clock source.
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*/
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#if !defined(STM32_TIM1SEL) || defined(__DOXYGEN__)
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#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
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#if !defined(STM32_I2S23SEL) || defined(__DOXYGEN__)
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#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
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#endif
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/**
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* @brief TIM15 clock source.
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* @brief FDCAN clock source.
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*/
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#if !defined(STM32_TIM15SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_TIM15SEL STM32_TIM15SEL_TIMPCLK
|
||||
#if !defined(STM32_FDCANSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_FDCANSEL STM32_FDCANSEL_HSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RNG clock source.
|
||||
* @brief CLK48 clock source.
|
||||
*/
|
||||
#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_RNGSEL STM32_RNGSEL_HSI16
|
||||
#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RNG divider value.
|
||||
* @brief ADC12 clock source.
|
||||
*/
|
||||
#if !defined(STM32_RNGDIV_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_RNGDIV_VALUE 1
|
||||
#if !defined(STM32_ADC12SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC clock source.
|
||||
* @brief ADC34 clock source.
|
||||
*/
|
||||
#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
|
||||
#if !defined(STM32_ADC34SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC34SEL STM32_ADC34SEL_PLLPCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief QSPI clock source.
|
||||
*/
|
||||
#if !defined(STM32_QSPISEL) || defined(__DOXYGEN__)
|
||||
#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -562,22 +628,41 @@
|
|||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
* - STM32G431xx, STM32G441xx, STM32G471xx.
|
||||
* - STM32G473xx, STM32G483xx.
|
||||
* - STM32G474xx, STM32G484xx.
|
||||
* - STM32GBK1CB.
|
||||
|
||||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(STM32G0xx_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G0xx_MCUCONF not defined"
|
||||
#if !defined(STM32G4xx_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G4xx_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32G070xx) && !defined(STM32G070_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G070_MCUCONF not defined"
|
||||
#if defined(STM32G431xx) && !defined(STM32G431_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G431_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32G071xx) && !defined(STM32G071_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G071_MCUCONF not defined"
|
||||
#if defined(STM32G441xx) && !defined(STM32G441_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G441_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32G081xx) && !defined(STM32G081_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G071_MCUCONF not defined"
|
||||
#if defined(STM32G471xx) && !defined(STM32G471_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G471_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32G473xx) && !defined(STM32G473_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G473_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32G483xx) && !defined(STM32G473_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G483_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32G474xx) && !defined(STM32G474_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G474_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32G484xx) && !defined(STM32G484_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32G484_MCUCONF not defined"
|
||||
|
||||
#elif defined(STM32GBK1CB) && !defined(STM32GBK1CB_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32GBK1CB_MCUCONF not defined"
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue