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F4x PLL clock checking fixed. According to RM0090 the value of PLLN may be between 64 and 432. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4740 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2012-10-11 17:57:18 +00:00
parent 980fa49caf
commit 82d5cb36c3
1 changed files with 1 additions and 1 deletions
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2
os/hal/platforms/STM32F4xx/hal_lld.h
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@ -986,7 +986,7 @@
/**
* @brief STM32_PLLN field.
*/
#if ((STM32_PLLN_VALUE >= 192) && (STM32_PLLN_VALUE <= 432)) || \
#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
defined(__DOXYGEN__)
#define STM32_PLLN (STM32_PLLN_VALUE << 6)
#else