diff --git a/os/hal/boards/ST_NUCLEO144_L496ZG/board.h b/os/hal/boards/ST_NUCLEO144_L496ZG/board.h
index 644d95edd..a30e7f005 100644
--- a/os/hal/boards/ST_NUCLEO144_L496ZG/board.h
+++ b/os/hal/boards/ST_NUCLEO144_L496ZG/board.h
@@ -204,6 +204,23 @@
#define GPIOH_PIN14 14U
#define GPIOH_PIN15 15U
+#define GPIOI_PIN0 0U
+#define GPIOI_PIN1 1U
+#define GPIOI_PIN2 2U
+#define GPIOI_PIN3 3U
+#define GPIOI_PIN4 4U
+#define GPIOI_PIN5 5U
+#define GPIOI_PIN6 6U
+#define GPIOI_PIN7 7U
+#define GPIOI_PIN8 8U
+#define GPIOI_PIN9 9U
+#define GPIOI_PIN10 10U
+#define GPIOI_PIN11 11U
+#define GPIOI_PIN12 12U
+#define GPIOI_PIN13 13U
+#define GPIOI_PIN14 14U
+#define GPIOI_PIN15 15U
+
/*
* IO lines assignments.
*/
@@ -1461,6 +1478,155 @@
PIN_LOCKR_DISABLED(GPIOH_PIN14) | \
PIN_LOCKR_DISABLED(GPIOH_PIN15))
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (analog).
+ * PI1 - PIN1 (analog).
+ * PI2 - PIN2 (input floating).
+ * PI3 - PIN3 (input floating).
+ * PI4 - PIN4 (input floating).
+ * PI5 - PIN5 (input floating).
+ * PI6 - PIN6 (input floating).
+ * PI7 - PIN7 (input floating).
+ * PI8 - PIN8 (input floating).
+ * PI9 - PIN9 (input floating).
+ * PI10 - PIN10 (input floating).
+ * PI11 - PIN11 (input floating).
+ * PI12 - PIN12 (input floating).
+ * PI13 - PIN13 (input floating).
+ * PI14 - PIN14 (input floating).
+ * PI15 - PIN15 (input floating).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_ANALOG(GPIOI_PIN0) | \
+ PIN_MODE_ANALOG(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_LOW(GPIOI_PIN0) | \
+ PIN_ODR_LOW(GPIOI_PIN1) | \
+ PIN_ODR_LOW(GPIOI_PIN2) | \
+ PIN_ODR_LOW(GPIOI_PIN3) | \
+ PIN_ODR_LOW(GPIOI_PIN4) | \
+ PIN_ODR_LOW(GPIOI_PIN5) | \
+ PIN_ODR_LOW(GPIOI_PIN6) | \
+ PIN_ODR_LOW(GPIOI_PIN7) | \
+ PIN_ODR_LOW(GPIOI_PIN8) | \
+ PIN_ODR_LOW(GPIOI_PIN9) | \
+ PIN_ODR_LOW(GPIOI_PIN10) | \
+ PIN_ODR_LOW(GPIOI_PIN11) | \
+ PIN_ODR_LOW(GPIOI_PIN12) | \
+ PIN_ODR_LOW(GPIOI_PIN13) | \
+ PIN_ODR_LOW(GPIOI_PIN14) | \
+ PIN_ODR_LOW(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
+#define VAL_GPIOI_ASCR (PIN_ASCR_DISABLED(GPIOI_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOI_PIN15))
+#define VAL_GPIOI_LOCKR (PIN_LOCKR_DISABLED(GPIOI_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOI_PIN15))
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/boards/ST_NUCLEO144_L496ZG/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO144_L496ZG/cfg/board.chcfg
index fc7fdacc8..a77c1ad7e 100644
--- a/os/hal/boards/ST_NUCLEO144_L496ZG/cfg/board.chcfg
+++ b/os/hal/boards/ST_NUCLEO144_L496ZG/cfg/board.chcfg
@@ -416,5 +416,55 @@
PinLock="Disabled" Alternate="0" ID="" Resistor="Floating"
Mode="Input" Level="Low" />
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
index bde4310d3..167bbb98c 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -93,16 +93,16 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
-#define STM32_PLLSAI1N_VALUE 60
+#define STM32_PLLSAI1N_VALUE 48
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
-#define STM32_PLLSAI1Q_VALUE 6
+#define STM32_PLLSAI1Q_VALUE 4
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
-#define STM32_PLLSAI2N_VALUE 60
+#define STM32_PLLSAI2N_VALUE 48
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
-#define STM32_PLLSAI2Q_VALUE 6
+#define STM32_PLLSAI2Q_VALUE 4
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
diff --git a/tools/ftl/schema/boards/stm32l4xx_board.xsd b/tools/ftl/schema/boards/stm32l4xx_board.xsd
index 3924650ed..5961e50da 100644
--- a/tools/ftl/schema/boards/stm32l4xx_board.xsd
+++ b/tools/ftl/schema/boards/stm32l4xx_board.xsd
@@ -14,6 +14,7 @@
+