diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/debug/RT-STM32L552ZE-NUCLEO144-TZ_HOST (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/debug/RT-STM32L552ZE-NUCLEO144-TZ_HOST (OpenOCD, Flash and Run).launch
new file mode 100644
index 000000000..f37a9711c
--- /dev/null
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/debug/RT-STM32L552ZE-NUCLEO144-TZ_HOST (OpenOCD, Flash and Run).launch
@@ -0,0 +1,52 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/debug/RT-STM32L552ZE-NUCLEO144-TZ_HOST (ST-Link GDB Server, Flash and Run).launch b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/debug/RT-STM32L552ZE-NUCLEO144-TZ_HOST (ST-Link GDB Server, Flash and Run).launch
new file mode 100644
index 000000000..24efddcfa
--- /dev/null
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TZ_HOST/debug/RT-STM32L552ZE-NUCLEO144-TZ_HOST (ST-Link GDB Server, Flash and Run).launch
@@ -0,0 +1,55 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S b/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
index 68e50679d..1a90811f8 100644
--- a/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
+++ b/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
@@ -226,8 +226,6 @@ _zombies: b _zombies
.thumb_func
.globl __port_ns_boot
__port_ns_boot:
- movs r1, #0
- movs r2, #0
movs r3, #0
movs r4, #0
movs r5, #0
@@ -257,32 +255,18 @@ __port_ns_boot:
vldr.64 d14, =0
vldr.64 d15, =0
#endif
-#if 0
+ msr BASEPRI, r3 /* Allowing NS-PendSV in NS state.*/
msr PSPLIM_NS, r3
msr MSPLIM_NS, r3
- msr BASEPRI, r3
- ldr r1, =SCB_VTOR_NS
+ ldr r1, = SCB_VTOR_NS
str r0, [r1, #0]
- ldr r1, [r0, #0] /* MSP from vectors table.*/
+ ldr r1, [r0, #0]
msr MSP_NS, r1
- ldr r2, [r0, #4] /* PC from vectors table.*/
- ldr r3, =0x30000000
- str r0, [r3, #0]
- str r1, [r3, #4]
- str r2, [r3, #8]
- bxns r2
-#else
- msr BASEPRI, r1 /* Allowing NS-PendSV.*/
- msr PSPLIM_NS, r1
- msr MSPLIM_NS, r1
- ldr r1, =0x20009000
- msr MSP_NS, r1
- ldr r1, =0x20009400
- msr PSP_NS, r1
- blxns r0
+ ldr r2, [r0, #4]
+ bic r2, #1
+ blxns r2
b chThdExit
#endif
-#endif
#endif /* !defined(__DOXYGEN__) */
diff --git a/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc b/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc
index f77e22201..dc91b2fd2 100644
--- a/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc
+++ b/os/hal/ports/STM32/STM32L5xx/stm32_secure.inc
@@ -49,18 +49,6 @@
#include "secconf.h"
/* Checks on configurations.*/
-#if !defined(STM32_FLASH_OVERRIDE_SETTINGS)
-#error "STM32_FLASH_OVERRIDE_SETTINGS not defined in secconf.h"
-#endif
-
-#if !defined(STM32_FLASH_SECWM1R1)
-#error "STM32_FLASH_SECWM1R1 not defined in secconf.h"
-#endif
-
-#if !defined(STM32_FLASH_SECWM2R1)
-#error "STM32_FLASH_SECWM2R1 not defined in secconf.h"
-#endif
-
#if !defined(STM32_FLASH_SECBB1R1)
#error "STM32_FLASH_SECBB1R1 not defined in secconf.h"
#endif
@@ -256,9 +244,6 @@
static inline void secure_init(void) {
#if STM32_SECURE_MODE
-#if STM32_FLASH_OVERRIDE_SETTINGS
-// FLASH->SECWM1R1 = STM32_FLASH_SECWM1R1;
-// FLASH->SECWM2R1 = STM32_FLASH_SECWM2R1;
FLASH->SECBB1R1 = STM32_FLASH_SECBB1R1;
FLASH->SECBB1R2 = STM32_FLASH_SECBB1R2;
FLASH->SECBB1R3 = STM32_FLASH_SECBB1R3;
@@ -267,7 +252,6 @@ static inline void secure_init(void) {
FLASH->SECBB2R2 = STM32_FLASH_SECBB2R2;
FLASH->SECBB2R3 = STM32_FLASH_SECBB2R3;
FLASH->SECBB2R4 = STM32_FLASH_SECBB2R4;
-#endif
GTZC_MPCBB1->VCTR[0] = STM32_MPCBB1_VCTR0;
GTZC_MPCBB1->VCTR[1] = STM32_MPCBB1_VCTR1;