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Ports setup PAL support for STM32. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1048 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2009-06-21 16:34:05 +00:00
parent 3bc7ecd47b
commit 85118e378c
6 changed files with 449 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
demos/ARMCM3-STM32F103-GCC/Makefile
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@ -64,6 +64,7 @@ include ../../test/test.mk
CSRC = ../../ports/ARMCM3/chcore.c \
../../ports/ARMCM3/nvic.c \
../../ports/ARMCM3-STM32F103/stm32_serial.c \
../../ports/ARMCM3-STM32F103/pal_lld.c \
${KERNSRC} \
${TESTSRC} \
../../src/lib/pal.c \

25
demos/ARMCM3-STM32F103-GCC/board.c
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@ -24,6 +24,17 @@
#include "board.h"
#include "stm32_serial.h"
/*
* Digital I/O ports static configuration as defined in @p board.h.
*/
static const STM32GPIOConfig config =
{
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
};
/*
* Early initialization code.
* This initialization is performed just after reset before BSS and DATA
@ -62,19 +73,7 @@ void hwinit0(void) {
/*
* I/O ports initialization as specified in board.h.
*/
palInit();
pal_lld_stm32_setup(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL);
palWritePort(IOPORT_A, VAL_GPIOAODR);
pal_lld_stm32_setup(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL);
palWritePort(IOPORT_B, VAL_GPIOBODR);
pal_lld_stm32_setup(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL);
palWritePort(IOPORT_C, VAL_GPIOCODR);
pal_lld_stm32_setup(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL);
palWritePort(IOPORT_D, VAL_GPIODODR);
palInit(&config);
}
/*

37
demos/ARMCM3-STM32F103-GCC/board.h
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@ -28,6 +28,7 @@
#undef FALSE
#undef TRUE
#include "stm32f10x_map.h"
#include "stm32f10x_rcc.h"
#define FALSE 0
#define TRUE (!FALSE)
#endif
@ -121,31 +122,31 @@
/*
* IO pins assignments.
*/
#define GPIOA_BUTTON 0
#define GPIOA_BUTTON 0
#define GPIOC_MMCWP 6
#define GPIOC_MMCCP 7
#define GPIOC_CANCNTL 10
#define GPIOC_DISC 11
#define GPIOC_LED 12
#define GPIOC_MMCWP 6
#define GPIOC_MMCCP 7
#define GPIOC_CANCNTL 10
#define GPIOC_DISC 11
#define GPIOC_LED 12
/*
* All inputs with pullups unless otherwise specified.
*/
#define VAL_GPIOACRL 0x88888884 // PA0:FI
#define VAL_GPIOACRH 0x88888888
#define VAL_GPIOAODR 0xFFFFFFFF
#define VAL_GPIOACRL 0x88888884 // PA0:FI
#define VAL_GPIOACRH 0x88888888
#define VAL_GPIOAODR 0xFFFFFFFF
#define VAL_GPIOBCRL 0x88883888 // PB3:PP
#define VAL_GPIOBCRH 0x88888888
#define VAL_GPIOBODR 0xFFFFFFFF
#define VAL_GPIOBCRL 0x88883888 // PB3:PP
#define VAL_GPIOBCRH 0x88888888
#define VAL_GPIOBODR 0xFFFFFFFF
#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI
#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP
#define VAL_GPIOCODR 0xFFFFFFFF
#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI
#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP
#define VAL_GPIOCODR 0xFFFFFFFF
#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI
#define VAL_GPIODCRH 0x88888888
#define VAL_GPIODODR 0xFFFFFFFF
#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI
#define VAL_GPIODCRH 0x88888888
#define VAL_GPIODODR 0xFFFFFFFF
#endif /* _BOARD_H_ */

288
demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h Normal file
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@ -0,0 +1,288 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rcc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* RCC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
#define __STM32F10x_RCC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 SYSCLK_Frequency;
u32 HCLK_Frequency;
u32 PCLK1_Frequency;
u32 PCLK2_Frequency;
u32 ADCCLK_Frequency;
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/* HSE configuration */
#define RCC_HSE_OFF ((u32)0x00000000)
#define RCC_HSE_ON ((u32)0x00010000)
#define RCC_HSE_Bypass ((u32)0x00040000)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/* PLL entry clock source */
#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
((SOURCE) == RCC_PLLSource_HSE_Div2))
/* PLL multiplication factor */
#define RCC_PLLMul_2 ((u32)0x00000000)
#define RCC_PLLMul_3 ((u32)0x00040000)
#define RCC_PLLMul_4 ((u32)0x00080000)
#define RCC_PLLMul_5 ((u32)0x000C0000)
#define RCC_PLLMul_6 ((u32)0x00100000)
#define RCC_PLLMul_7 ((u32)0x00140000)
#define RCC_PLLMul_8 ((u32)0x00180000)
#define RCC_PLLMul_9 ((u32)0x001C0000)
#define RCC_PLLMul_10 ((u32)0x00200000)
#define RCC_PLLMul_11 ((u32)0x00240000)
#define RCC_PLLMul_12 ((u32)0x00280000)
#define RCC_PLLMul_13 ((u32)0x002C0000)
#define RCC_PLLMul_14 ((u32)0x00300000)
#define RCC_PLLMul_15 ((u32)0x00340000)
#define RCC_PLLMul_16 ((u32)0x00380000)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/* System clock source */
#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/* AHB clock source */
#define RCC_SYSCLK_Div1 ((u32)0x00000000)
#define RCC_SYSCLK_Div2 ((u32)0x00000080)
#define RCC_SYSCLK_Div4 ((u32)0x00000090)
#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/* APB1/APB2 clock source */
#define RCC_HCLK_Div1 ((u32)0x00000000)
#define RCC_HCLK_Div2 ((u32)0x00000400)
#define RCC_HCLK_Div4 ((u32)0x00000500)
#define RCC_HCLK_Div8 ((u32)0x00000600)
#define RCC_HCLK_Div16 ((u32)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/* RCC Interrupt source */
#define RCC_IT_LSIRDY ((u8)0x01)
#define RCC_IT_LSERDY ((u8)0x02)
#define RCC_IT_HSIRDY ((u8)0x04)
#define RCC_IT_HSERDY ((u8)0x08)
#define RCC_IT_PLLRDY ((u8)0x10)
#define RCC_IT_CSS ((u8)0x80)
#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))
/* USB clock source */
#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/* ADC clock source */
#define RCC_PCLK2_Div2 ((u32)0x00000000)
#define RCC_PCLK2_Div4 ((u32)0x00004000)
#define RCC_PCLK2_Div6 ((u32)0x00008000)
#define RCC_PCLK2_Div8 ((u32)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
/* LSE configuration */
#define RCC_LSE_OFF ((u8)0x00)
#define RCC_LSE_ON ((u8)0x01)
#define RCC_LSE_Bypass ((u8)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/* RTC clock source */
#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
/* AHB peripheral */
#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)
#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)
#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
#define RCC_AHBPeriph_CRC ((u32)0x00000040)
#define RCC_AHBPeriph_FSMC ((u32)0x00000100)
#define RCC_AHBPeriph_SDIO ((u32)0x00000400)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
/* APB2 peripheral */
#define RCC_APB2Periph_AFIO ((u32)0x00000001)
#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
#define RCC_APB2Periph_GPIOF ((u32)0x00000080)
#define RCC_APB2Periph_GPIOG ((u32)0x00000100)
#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
#define RCC_APB2Periph_TIM8 ((u32)0x00002000)
#define RCC_APB2Periph_USART1 ((u32)0x00004000)
#define RCC_APB2Periph_ADC3 ((u32)0x00008000)
#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
/* APB1 peripheral */
#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
#define RCC_APB1Periph_TIM5 ((u32)0x00000008)
#define RCC_APB1Periph_TIM6 ((u32)0x00000010)
#define RCC_APB1Periph_TIM7 ((u32)0x00000020)
#define RCC_APB1Periph_WWDG ((u32)0x00000800)
#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
#define RCC_APB1Periph_SPI3 ((u32)0x00008000)
#define RCC_APB1Periph_USART2 ((u32)0x00020000)
#define RCC_APB1Periph_USART3 ((u32)0x00040000)
#define RCC_APB1Periph_UART4 ((u32)0x00080000)
#define RCC_APB1Periph_UART5 ((u32)0x00100000)
#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
#define RCC_APB1Periph_USB ((u32)0x00800000)
#define RCC_APB1Periph_CAN ((u32)0x02000000)
#define RCC_APB1Periph_BKP ((u32)0x08000000)
#define RCC_APB1Periph_PWR ((u32)0x10000000)
#define RCC_APB1Periph_DAC ((u32)0x20000000)
#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
/* Clock source to output on MCO pin */
#define RCC_MCO_NoClock ((u8)0x00)
#define RCC_MCO_SYSCLK ((u8)0x04)
#define RCC_MCO_HSI ((u8)0x05)
#define RCC_MCO_HSE ((u8)0x06)
#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2))
/* RCC Flag */
#define RCC_FLAG_HSIRDY ((u8)0x21)
#define RCC_FLAG_HSERDY ((u8)0x31)
#define RCC_FLAG_PLLRDY ((u8)0x39)
#define RCC_FLAG_LSERDY ((u8)0x41)
#define RCC_FLAG_LSIRDY ((u8)0x61)
#define RCC_FLAG_PINRST ((u8)0x7A)
#define RCC_FLAG_PORRST ((u8)0x7B)
#define RCC_FLAG_SFTRST ((u8)0x7C)
#define RCC_FLAG_IWDGRST ((u8)0x7D)
#define RCC_FLAG_WWDGRST ((u8)0x7E)
#define RCC_FLAG_LPWRRST ((u8)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RCC_DeInit(void);
void RCC_HSEConfig(u32 RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
u8 RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(u32 RCC_SYSCLK);
void RCC_PCLK1Config(u32 RCC_HCLK);
void RCC_PCLK2Config(u32 RCC_HCLK);
void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
void RCC_ADCCLKConfig(u32 RCC_PCLK2);
void RCC_LSEConfig(u8 RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(u8 RCC_MCO);
FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(u8 RCC_IT);
void RCC_ClearITPendingBit(u8 RCC_IT);
#endif /* __STM32F10x_RCC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

139
ports/ARMCM3-STM32F103/pal_lld.h
View File

@ -19,7 +19,7 @@
/**
* @file ports/ARMCM3-STM32F103/pal_lld.h
* @brief STM32 GPIO low level driver
* @brief STM32 GPIO low level driver header
* @addtogroup STM32F103_PAL
* @{
*/
@ -35,6 +35,7 @@
#undef FALSE
#undef TRUE
#include "stm32f10x_map.h"
#include "stm32f10x_rcc.h"
#define FALSE 0
#define TRUE (!FALSE)
#endif
@ -43,11 +44,67 @@
/* I/O Ports Types and constants. */
/*===========================================================================*/
/**
* @brief GPIO port setup info.
*/
typedef struct {
/** Initial value for ODR register.*/
uint32_t odr;
/** Initial value for CRL register.*/
uint32_t crl;
/** Initial value for CRH register.*/
uint32_t crh;
} stm32_gpio_setup_t;
/**
* @brief STM32 GPIO static initializer.
* @details An instance of this structure must be passed to @p palInit() at
* system startup time in order to initialized the digital I/O
* subsystem. This represents only the initial setup, specific pads
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
#if defined(_GPIOA) || defined(__DOXYGEN__)
/** @brief Port A setup data.*/
stm32_gpio_setup_t PAData;
#endif
#if defined(_GPIOB) || defined(__DOXYGEN__)
/** @brief Port B setup data.*/
stm32_gpio_setup_t PBData;
#endif
#if defined(_GPIOC) || defined(__DOXYGEN__)
/** @brief Port C setup data.*/
stm32_gpio_setup_t PCData;
#endif
#if defined(_GPIOD) || defined(__DOXYGEN__)
/** @brief Port D setup data.*/
stm32_gpio_setup_t PDData;
#endif
#if defined(_GPIOE) || defined(__DOXYGEN__)
/** @brief Port E setup data.*/
stm32_gpio_setup_t PEData;
#endif
#if defined(_GPIOF) || defined(__DOXYGEN__)
/** @brief Port F setup data.*/
stm32_gpio_setup_t PFData;
#endif
#if defined(_GPIOG) || defined(__DOXYGEN__)
/** @brief Port G setup data.*/
stm32_gpio_setup_t PGData;
#endif
} STM32GPIOConfig;
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 16
/**
* @brief Whole port mask.
* @brief This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
/**
* @brief Digital I/O port sized unsigned type.
*/
@ -75,33 +132,47 @@ typedef GPIO_TypeDef * ioportid_t;
#endif
/**
* @brief GPIO port A identifier.
* @brief GPIO port B identifier.
*/
#if defined(_GPIOB) || defined(__DOXYGEN__)
#define IOPORT_B GPIOB
#endif
/**
* @brief GPIO port A identifier.
* @brief GPIO port C identifier.
*/
#if defined(_GPIOC) || defined(__DOXYGEN__)
#define IOPORT_C GPIOC
#endif
/**
* @brief GPIO port A identifier.
* @brief GPIO port D identifier.
*/
#if defined(_GPIOD) || defined(__DOXYGEN__)
#define IOPORT_D GPIOD
#endif
/**
* @brief GPIO port A identifier.
* @brief GPIO port E identifier.
*/
#if defined(_GPIOE) || defined(__DOXYGEN__)
#define IOPORT_E GPIOE
#endif
/**
* @brief GPIO port F identifier.
*/
#if defined(_GPIOF) || defined(__DOXYGEN__)
#define IOPORT_F GPIOF
#endif
/**
* @brief GPIO port G identifier.
*/
#if defined(_GPIOG) || defined(__DOXYGEN__)
#define IOPORT_G GPIOG
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, please put them in a file named ioports_lld.c if so. */
@ -109,13 +180,8 @@ typedef GPIO_TypeDef * ioportid_t;
/**
* @brief GPIO ports subsystem initialization.
* @details Ports A-D enabled, AFIO enabled.
*/
#define pal_lld_init() { \
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | \
RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | \
RCC_APB2ENR_IOPDEN; \
}
#define pal_lld_init(config) _pal_lld_init(config)
/**
* @brief Reads an I/O port.
@ -153,6 +219,9 @@ typedef GPIO_TypeDef * ioportid_t;
*
* @note This function is not meant to be invoked directly by the application
* code.
* @note Writing on pads programmed as pull-up or pull-down has the side
* effect to modify the resistor setting because the output latched data
* is used for the resistor selection.
*/
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
@ -166,6 +235,9 @@ typedef GPIO_TypeDef * ioportid_t;
*
* @note This function is not meant to be invoked directly by the application
* code.
* @note Writing on pads programmed as pull-up or pull-down has the side
* effect to modify the resistor setting because the output latched data
* is used for the resistor selection.
*/
#define pal_lld_setport(port, bits) ((port)->BSRR = (bits))
@ -179,6 +251,9 @@ typedef GPIO_TypeDef * ioportid_t;
*
* @note This function is not meant to be invoked directly by the application
* code.
* @note Writing on pads programmed as pull-up or pull-down has the side
* effect to modify the resistor setting because the output latched data
* is used for the resistor selection.
*/
#define pal_lld_clearport(port, bits) ((port)->BRR = (bits))
@ -195,12 +270,33 @@ typedef GPIO_TypeDef * ioportid_t;
*
* @note This function is not meant to be invoked directly by the application
* code.
* @note Writing on pads programmed as pull-up or pull-down has the side
* effect to modify the resistor setting because the output latched data
* is used for the resistor selection.
*/
#define pal_lld_writegroup(port, mask, offset, bits) { \
(port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \
(((bits) & (mask)) << (offset)); \
}
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
*
* @param[in] port the port identifier
* @param[in] mask the group mask
* @param[in] mode the mode
*
* @note This function is not meant to be invoked directly by the application
* code.
* @note Writing on pads programmed as pull-up or pull-down has the side
* effect to modify the resistor setting because the output latched data
* is used for the resistor selection.
*/
#define pal_lld_setgroupmode(port, mask, mode) \
_pal_lld_setgroupmode(port, mask, mode)
/**
* @brief Writes a logical state on an output pad.
*
@ -210,19 +306,22 @@ typedef GPIO_TypeDef * ioportid_t;
*
* @note This function is not meant to be invoked directly by the application
* code.
* @note Writing on pads programmed as pull-up or pull-down has the side
* effect to modify the resistor setting because the output latched data
* is used for the resistor selection.
*/
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
/**
* @brief GPIO port setup.
* @details This function initializes a GPIO port, note that this functionality
* is STM32 specific and non portable. It does not have a
* corresponding PAL API.
*/
#define pal_lld_stm32_setup(port, crh, crl) { \
(port)->CRH = (crh); \
(port)->CRL = (crl); \
#ifdef __cplusplus
extern "C" {
#endif
void _pal_lld_init(const STM32GPIOConfig *config);
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
uint_fast8_t mode);
#ifdef __cplusplus
}
#endif
#endif /* _PAL_LLD_H_ */

15
ports/ARMCM3-STM32F103/port.dox
View File

@ -31,17 +31,22 @@
/**
* @defgroup STM32F103_PAL I/O Ports Support
* @brief I/O Ports peripherals support.
* @details This module supports the STM32F103 GPIO controller. The STM32
* controller is very flexible and allows to implement all the recommended
* behaviors for the I/O port driver. It supports the following features (see
* @ref PAL):
* @details This module supports the STM32F103 GPIO controller. The controller
* supports the following features (see @ref PAL):
* - 16 bits wide ports.
* - Atomic set/reset functions.
* - Atomic set+reset function (atomic bus operations).
* - Output latched regardless of the pad setting.
* - Direct read of input pads regardless of the pad setting.
* .
* The only non atomic operation is bit toggling.
* <h2>Undesiderable Behavior</h2>
* Some GPIO features are less than optimal:
* - Pad/group/port toggling operations are not atomic.
* - Pad/group mode setup is not atomic.
* - Writing on pads/groups/ports programmed as input with pull-up/down
* resistor can change the resistor setting because the output latch is
* used for resistor selection.
* .
* @ingroup STM32F103
*/