Added STM32 ADCv4 placeholders.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11262 35acf78f-673a-0410-8e92-d51de3d6d3f4
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85becea5ec
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ifeq ($(USE_SMART_BUILD),yes)
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ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
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endif
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else
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
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endif
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PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv4
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@ -0,0 +1,973 @@
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/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADCv3/hal_adc_lld.c
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* @brief STM32 ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define ADC1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
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#define ADC2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
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#define ADC3_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
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#define ADC4_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_CHN)
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#if STM32_ADC_DUAL_MODE
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#if STM32_ADC_COMPACT_SAMPLES
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/* Compact type dual mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
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#define ADC_DMA_MDMA ADC_CCR_MDMA_HWORD
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#else /* !STM32_ADC_COMPACT_SAMPLES */
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/* Large type dual mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
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#define ADC_DMA_MDMA ADC_CCR_MDMA_WORD
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#endif /* !STM32_ADC_COMPACT_SAMPLES */
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#else /* !STM32_ADC_DUAL_MODE */
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#if STM32_ADC_COMPACT_SAMPLES
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/* Compact type single mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
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#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED
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#else /* !STM32_ADC_COMPACT_SAMPLES */
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/* Large type single mode.*/
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#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
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#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED
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#endif /* !STM32_ADC_COMPACT_SAMPLES */
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#endif /* !STM32_ADC_DUAL_MODE */
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/** @brief ADC2 driver identifier.*/
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#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/** @brief ADC3 driver identifier.*/
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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ADCDriver ADCD3;
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#endif
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/** @brief ADC4 driver identifier.*/
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#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)
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ADCDriver ADCD4;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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static const ADCConfig default_config = {
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difsel: 0
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};
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static uint32_t clkmask;
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Enables the ADC voltage regulator.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_vreg_on(ADCDriver *adcp) {
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#if defined(STM32F3XX)
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adcp->adcm->CR = 0; /* RM 12.4.3.*/
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adcp->adcm->CR = ADC_CR_ADVREGEN_0;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = ADC_CR_ADVREGEN_0;
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#endif
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osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
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#endif
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#if defined(STM32L4XX)
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adcp->adcm->CR = 0; /* RM 16.3.6.*/
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adcp->adcm->CR = ADC_CR_ADVREGEN;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = ADC_CR_ADVREGEN;
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#endif
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osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
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#endif
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}
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/**
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* @brief Disables the ADC voltage regulator.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_vreg_off(ADCDriver *adcp) {
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#if defined(STM32F3XX)
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adcp->adcm->CR = 0; /* RM 12.4.3.*/
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adcp->adcm->CR = ADC_CR_ADVREGEN_1;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = 0;
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adcp->adcs->CR = ADC_CR_ADVREGEN_1;
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#endif
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#endif
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#if defined(STM32L4XX)
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adcp->adcm->CR = 0; /* RM 12.4.3.*/
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adcp->adcm->CR = ADC_CR_DEEPPWD;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR = 0;
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adcp->adcs->CR = ADC_CR_DEEPPWD;
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#endif
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#endif
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}
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/**
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* @brief Enables the ADC analog circuit.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_analog_on(ADCDriver *adcp) {
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#if defined(STM32F3XX)
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adcp->adcm->CR |= ADC_CR_ADEN;
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while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)
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;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR |= ADC_CR_ADEN;
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while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)
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;
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#endif
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#endif
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#if defined(STM32L4XX)
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adcp->adcm->CR |= ADC_CR_ADEN;
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while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
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;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR |= ADC_CR_ADEN;
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while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
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;
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#endif
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#endif
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}
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/**
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* @brief Disables the ADC analog circuit.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_analog_off(ADCDriver *adcp) {
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adcp->adcm->CR |= ADC_CR_ADDIS;
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while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
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;
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#if STM32_ADC_DUAL_MODE
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adcp->adcs->CR |= ADC_CR_ADDIS;
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while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
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;
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#endif
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}
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/**
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* @brief Calibrates and ADC unit.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_calibrate(ADCDriver *adcp) {
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#if defined(STM32F3XX)
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osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
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adcp->adcm->CR |= ADC_CR_ADCAL;
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while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
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;
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#if STM32_ADC_DUAL_MODE
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osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
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adcp->adcs->CR |= ADC_CR_ADCAL;
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while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
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;
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#endif
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#endif
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#if defined(STM32L4XX)
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osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state");
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adcp->adcm->CR |= ADC_CR_ADCAL;
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while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
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;
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#if STM32_ADC_DUAL_MODE
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osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state");
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adcp->adcs->CR |= ADC_CR_ADCAL;
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while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
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;
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#endif
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#endif
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}
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/**
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* @brief Stops an ongoing conversion, if any.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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static void adc_lld_stop_adc(ADCDriver *adcp) {
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if (adcp->adcm->CR & ADC_CR_ADSTART) {
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adcp->adcm->CR |= ADC_CR_ADSTP;
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while (adcp->adcm->CR & ADC_CR_ADSTP)
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;
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}
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}
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA, this could help only if the DMA tries to access an unmapped
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address space or violates alignment rules.*/
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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else {
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/* It is possible that the conversion group has already be reset by the
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ADC error handler, in this case this interrupt is spurious.*/
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if (adcp->grpp != NULL) {
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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}
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}
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}
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/**
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* @brief ADC ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] isr content of the ISR register
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*/
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static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
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/* It could be a spurious interrupt caused by overflows after DMA disabling,
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just ignore it in this case.*/
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if (adcp->grpp != NULL) {
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((isr & ADC_ISR_OVR) &&
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(dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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_adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
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}
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if (isr & ADC_ISR_AWD1) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD1);
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}
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if (isr & ADC_ISR_AWD2) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD2);
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}
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if (isr & ADC_ISR_AWD3) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD3);
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
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/**
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* @brief ADC1/ADC2 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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#if STM32_ADC_DUAL_MODE
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isr = ADC1->ISR;
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isr |= ADC2->ISR;
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ADC1->ISR = isr;
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ADC2->ISR = isr;
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#if defined(STM32_ADC_ADC12_IRQ_HOOK)
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STM32_ADC_ADC12_IRQ_HOOK
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#endif
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adc_lld_serve_interrupt(&ADCD1, isr);
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#else /* !STM32_ADC_DUAL_MODE */
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#if STM32_ADC_USE_ADC1
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isr = ADC1->ISR;
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ADC1->ISR = isr;
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#if defined(STM32_ADC_ADC1_IRQ_HOOK)
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STM32_ADC_ADC1_IRQ_HOOK
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#endif
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adc_lld_serve_interrupt(&ADCD1, isr);
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#endif
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#if STM32_ADC_USE_ADC2
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isr = ADC2->ISR;
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ADC2->ISR = isr;
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#if defined(STM32_ADC_ADC2_IRQ_HOOK)
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STM32_ADC_ADC2_IRQ_HOOK
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#endif
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adc_lld_serve_interrupt(&ADCD2, isr);
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#endif
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#endif /* !STM32_ADC_DUAL_MODE */
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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/**
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* @brief ADC3 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_ADC3_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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isr = ADC3->ISR;
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ADC3->ISR = isr;
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#if defined(STM32_ADC_ADC3_IRQ_HOOK)
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STM32_ADC_ADC3_IRQ_HOOK
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#endif
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adc_lld_serve_interrupt(&ADCD3, isr);
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OSAL_IRQ_EPILOGUE();
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}
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#if STM32_ADC_DUAL_MODE
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/**
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* @brief ADC4 interrupt handler (as ADC3 slave).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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isr = ADC4->ISR;
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ADC4->ISR = isr;
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adc_lld_serve_interrupt(&ADCD3, isr);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_ADC_DUAL_MODE */
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#endif /* STM32_ADC_USE_ADC3 */
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#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)
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/**
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* @brief ADC4 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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isr = ADC4->ISR;
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ADC4->ISR = isr;
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adc_lld_serve_interrupt(&ADCD4, isr);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_ADC_USE_ADC4 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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clkmask = 0;
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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#if defined(ADC1_2_COMMON)
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ADCD1.adcc = ADC1_2_COMMON;
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#elif defined(ADC123_COMMON)
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ADCD1.adcc = ADC123_COMMON;
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#else
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ADCD1.adcc = ADC1_COMMON;
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#endif
|
||||
ADCD1.adcm = ADC1;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
ADCD1.adcs = ADC2;
|
||||
#endif
|
||||
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
|
||||
ADCD1.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#if STM32_ADC_USE_ADC2
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD2);
|
||||
#if defined(ADC1_2_COMMON)
|
||||
ADCD2.adcc = ADC1_2_COMMON;
|
||||
#elif defined(ADC123_COMMON)
|
||||
ADCD2.adcc = ADC123_COMMON;
|
||||
#endif
|
||||
ADCD2.adcm = ADC2;
|
||||
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
|
||||
ADCD2.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC2 */
|
||||
|
||||
#if STM32_ADC_USE_ADC3
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD3);
|
||||
#if defined(ADC3_4_COMMON)
|
||||
ADCD3.adcc = ADC3_4_COMMON;
|
||||
#elif defined(ADC123_COMMON)
|
||||
ADCD1.adcc = ADC123_COMMON;
|
||||
#else
|
||||
ADCD3.adcc = ADC3_COMMON;
|
||||
#endif
|
||||
ADCD3.adcm = ADC3;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
ADCD3.adcs = ADC4;
|
||||
#endif
|
||||
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
|
||||
ADCD3.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#if STM32_ADC_USE_ADC4
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD4);
|
||||
ADCD4.adcc = ADC3_4_COMMON;
|
||||
ADCD4.adcm = ADC4;
|
||||
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
|
||||
ADCD4.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC4 */
|
||||
|
||||
/* IRQs setup.*/
|
||||
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
|
||||
nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC3
|
||||
nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
|
||||
#endif
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC4
|
||||
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* ADC units pre-initializations.*/
|
||||
#if defined(STM32F3XX)
|
||||
#if STM32_HAS_ADC1 && STM32_HAS_ADC2
|
||||
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
|
||||
rccEnableADC12(false);
|
||||
rccResetADC12();
|
||||
ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
rccDisableADC12();
|
||||
#endif
|
||||
#else
|
||||
#if STM32_ADC_USE_ADC1
|
||||
rccEnableADC12(false);
|
||||
rccResetADC12();
|
||||
ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
rccDisableADC12();
|
||||
#endif
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
|
||||
rccEnableADC34(false);
|
||||
rccResetADC34();
|
||||
ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
rccDisableADC34();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(false);
|
||||
rccResetADC123();
|
||||
|
||||
#if defined(ADC1_2_COMMON)
|
||||
ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#elif defined(ADC123_COMMON)
|
||||
ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#else
|
||||
ADC1_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
|
||||
rccDisableADC123();
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the ADC peripheral.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_start(ADCDriver *adcp) {
|
||||
|
||||
/* Handling the default configuration.*/
|
||||
if (adcp->config == NULL) {
|
||||
adcp->config = &default_config;
|
||||
}
|
||||
|
||||
/* If in stopped state then enables the ADC and DMA clocks.*/
|
||||
if (adcp->state == ADC_STOP) {
|
||||
#if STM32_ADC_USE_ADC1
|
||||
if (&ADCD1 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 0);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC12(false);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(false);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#if STM32_ADC_USE_ADC2
|
||||
if (&ADCD2 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 1);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC12(false);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(false);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC2 */
|
||||
|
||||
#if STM32_ADC_USE_ADC3
|
||||
if (&ADCD3 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 2);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC34(false);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(false);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#if STM32_ADC_USE_ADC4
|
||||
if (&ADCD4 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC4_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 3);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC34(false);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(false);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC4 */
|
||||
|
||||
/* Setting DMA peripheral-side pointer.*/
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
|
||||
#else
|
||||
dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
|
||||
#endif
|
||||
|
||||
/* Differential channels setting.*/
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcm->DIFSEL = adcp->config->difsel;
|
||||
adcp->adcs->DIFSEL = adcp->config->difsel;
|
||||
#else
|
||||
adcp->adcm->DIFSEL = adcp->config->difsel;
|
||||
#endif
|
||||
|
||||
/* Master ADC calibration.*/
|
||||
adc_lld_vreg_on(adcp);
|
||||
adc_lld_calibrate(adcp);
|
||||
|
||||
/* Master ADC enabled here in order to reduce conversions latencies.*/
|
||||
adc_lld_analog_on(adcp);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the ADC peripheral.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_stop(ADCDriver *adcp) {
|
||||
|
||||
/* If in ready state then disables the ADC clock and analog part.*/
|
||||
if (adcp->state == ADC_READY) {
|
||||
|
||||
/* Releasing the associated DMA channel.*/
|
||||
dmaStreamRelease(adcp->dmastp);
|
||||
|
||||
/* Stopping the ongoing conversion, if any.*/
|
||||
adc_lld_stop_adc(adcp);
|
||||
|
||||
/* Disabling ADC analog circuit and regulator.*/
|
||||
adc_lld_analog_off(adcp);
|
||||
adc_lld_vreg_off(adcp);
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC1
|
||||
if (&ADCD1 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2
|
||||
if (&ADCD2 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3
|
||||
if (&ADCD3 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 2);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4
|
||||
if (&ADCD4 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 3);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F3XX)
|
||||
#if STM32_HAS_ADC1 || STM32_HAS_ADC2
|
||||
if ((clkmask & 0x3) == 0) {
|
||||
rccDisableADC12();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC3 || STM32_HAS_ADC4
|
||||
if ((clkmask & 0xC) == 0) {
|
||||
rccDisableADC34();
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
if ((clkmask & 0x7) == 0) {
|
||||
rccDisableADC123();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts an ADC conversion.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_start_conversion(ADCDriver *adcp) {
|
||||
uint32_t dmamode, cfgr;
|
||||
const ADCConversionGroup *grpp = adcp->grpp;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
uint32_t ccr = grpp->ccr & ~(ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK);
|
||||
#endif
|
||||
|
||||
osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
|
||||
"odd number of channels in dual mode");
|
||||
|
||||
/* Calculating control registers values.*/
|
||||
dmamode = adcp->dmamode;
|
||||
cfgr = grpp->cfgr | ADC_CFGR_DMAEN;
|
||||
if (grpp->circular) {
|
||||
dmamode |= STM32_DMA_CR_CIRC;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
ccr |= ADC_CCR_DMACFG_CIRCULAR;
|
||||
#else
|
||||
cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
|
||||
#endif
|
||||
if (adcp->depth > 1) {
|
||||
/* If circular buffer depth > 1, then the half transfer interrupt
|
||||
is enabled in order to allow streaming processing.*/
|
||||
dmamode |= STM32_DMA_CR_HTIE;
|
||||
}
|
||||
}
|
||||
|
||||
/* DMA setup.*/
|
||||
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
|
||||
(uint32_t)adcp->depth);
|
||||
#else
|
||||
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
|
||||
(uint32_t)adcp->depth);
|
||||
#endif
|
||||
dmaStreamSetMode(adcp->dmastp, dmamode);
|
||||
dmaStreamEnable(adcp->dmastp);
|
||||
|
||||
/* ADC setup, if it is defined a callback for the analog watch dog then it
|
||||
is enabled.*/
|
||||
adcp->adcm->ISR = adcp->adcm->ISR;
|
||||
adcp->adcm->IER = ADC_IER_OVR | ADC_IER_AWD1;
|
||||
adcp->adcm->TR1 = grpp->tr1;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
|
||||
/* Configuring the CCR register with the user-specified settings
|
||||
in the conversion group configuration structure, static settings are
|
||||
preserved.*/
|
||||
adcp->adcc->CCR = (adcp->adcc->CCR &
|
||||
(ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK)) | ccr;
|
||||
|
||||
adcp->adcm->SMPR1 = grpp->smpr[0];
|
||||
adcp->adcm->SMPR2 = grpp->smpr[1];
|
||||
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
|
||||
adcp->adcm->SQR2 = grpp->sqr[1];
|
||||
adcp->adcm->SQR3 = grpp->sqr[2];
|
||||
adcp->adcm->SQR4 = grpp->sqr[3];
|
||||
adcp->adcs->SMPR1 = grpp->ssmpr[0];
|
||||
adcp->adcs->SMPR2 = grpp->ssmpr[1];
|
||||
adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
|
||||
adcp->adcs->SQR2 = grpp->ssqr[1];
|
||||
adcp->adcs->SQR3 = grpp->ssqr[2];
|
||||
adcp->adcs->SQR4 = grpp->ssqr[3];
|
||||
|
||||
#else /* !STM32_ADC_DUAL_MODE */
|
||||
adcp->adcm->SMPR1 = grpp->smpr[0];
|
||||
adcp->adcm->SMPR2 = grpp->smpr[1];
|
||||
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
|
||||
adcp->adcm->SQR2 = grpp->sqr[1];
|
||||
adcp->adcm->SQR3 = grpp->sqr[2];
|
||||
adcp->adcm->SQR4 = grpp->sqr[3];
|
||||
#endif /* !STM32_ADC_DUAL_MODE */
|
||||
|
||||
/* ADC configuration.*/
|
||||
adcp->adcm->CFGR = cfgr;
|
||||
|
||||
/* Starting conversion.*/
|
||||
adcp->adcm->CR |= ADC_CR_ADSTART;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops an ongoing conversion.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp) {
|
||||
|
||||
dmaStreamDisable(adcp->dmastp);
|
||||
adc_lld_stop_adc(adcp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the VREFEN bit.
|
||||
* @details The VREFEN bit is required in order to sample the VREF channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32EnableVREF(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR |= ADC_CCR_VREFEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the VREFEN bit.
|
||||
* @details The VREFEN bit is required in order to sample the VREF channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32DisableVREF(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR &= ~ADC_CCR_VREFEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the TSEN bit.
|
||||
* @details The TSEN bit is required in order to sample the internal
|
||||
* temperature sensor and internal reference voltage.
|
||||
* @note This is an STM32-only functionality.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32EnableTS(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR |= ADC_CCR_TSEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the TSEN bit.
|
||||
* @details The TSEN bit is required in order to sample the internal
|
||||
* temperature sensor and internal reference voltage.
|
||||
* @note This is an STM32-only functionality.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32DisableTS(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR &= ~ADC_CCR_TSEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the VBATEN bit.
|
||||
* @details The VBATEN bit is required in order to sample the VBAT channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32EnableVBAT(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR |= ADC_CCR_VBATEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the VBATEN bit.
|
||||
* @details The VBATEN bit is required in order to sample the VBAT channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32DisableVBAT(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR &= ~ADC_CCR_VBATEN;
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,850 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ADCv3/hal_adc_lld.h
|
||||
* @brief STM32 ADC subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HAL_ADC_LLD_H
|
||||
#define HAL_ADC_LLD_H
|
||||
|
||||
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Available analog channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
|
||||
#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
|
||||
#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
|
||||
#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
|
||||
#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
|
||||
#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
|
||||
#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
|
||||
#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
|
||||
#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
|
||||
#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
|
||||
#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
|
||||
#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
|
||||
#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
|
||||
#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
|
||||
#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
|
||||
#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
|
||||
#define ADC_CHANNEL_IN16 16 /**< @brief External analog input 16. */
|
||||
#define ADC_CHANNEL_IN17 17 /**< @brief External analog input 17. */
|
||||
#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rates
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F3XX)
|
||||
#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
|
||||
#define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_7P5 3 /**< @brief 20 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_19P5 4 /**< @brief 32 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_61P5 5 /**< @brief 74 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
#define ADC_SMPR_SMP_2P5 0 /**< @brief 15 cycles conversion time */
|
||||
#define ADC_SMPR_SMP_6P5 1 /**< @brief 19 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_12P5 2 /**< @brief 25 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_24P5 3 /**< @brief 37 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_47P5 4 /**< @brief 60 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_92P5 5 /**< @brief 105 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_247P5 6 /**< @brief 260 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_640P5 7 /**< @brief 653 cycles conversion time. */
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CFGR1_RES_12BIT (0 << 3)
|
||||
#define ADC_CFGR1_RES_10BIT (1 << 3)
|
||||
#define ADC_CFGR1_RES_8BIT (2 << 3)
|
||||
#define ADC_CFGR1_RES_6BIT (3 << 3)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CFGR register configuration helpers
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CFGR_DMACFG_MASK (1 << 1)
|
||||
#define ADC_CFGR_DMACFG_ONESHOT (0 << 1)
|
||||
#define ADC_CFGR_DMACFG_CIRCULAR (1 << 1)
|
||||
|
||||
#define ADC_CFGR_RES_MASK (3 << 3)
|
||||
#define ADC_CFGR_RES_12BITS (0 << 3)
|
||||
#define ADC_CFGR_RES_10BITS (1 << 3)
|
||||
#define ADC_CFGR_RES_8BITS (2 << 3)
|
||||
#define ADC_CFGR_RES_6BITS (3 << 3)
|
||||
|
||||
#define ADC_CFGR_ALIGN_MASK (1 << 5)
|
||||
#define ADC_CFGR_ALIGN_RIGHT (0 << 5)
|
||||
#define ADC_CFGR_ALIGN_LEFT (1 << 5)
|
||||
|
||||
#define ADC_CFGR_EXTSEL_MASK (15 << 6)
|
||||
#define ADC_CFGR_EXTSEL_SRC(n) ((n) << 6)
|
||||
|
||||
#define ADC_CFGR_EXTEN_MASK (3 << 10)
|
||||
#define ADC_CFGR_EXTEN_DISABLED (0 << 10)
|
||||
#define ADC_CFGR_EXTEN_RISING (1 << 10)
|
||||
#define ADC_CFGR_EXTEN_FALLING (2 << 10)
|
||||
#define ADC_CFGR_EXTEN_BOTH (3 << 10)
|
||||
|
||||
#define ADC_CFGR_DISCEN_MASK (1 << 16)
|
||||
#define ADC_CFGR_DISCEN_DISABLED (0 << 16)
|
||||
#define ADC_CFGR_DISCEN_ENABLED (1 << 16)
|
||||
|
||||
#define ADC_CFGR_DISCNUM_MASK (7 << 17)
|
||||
#define ADC_CFGR_DISCNUM_VAL(n) ((n) << 17)
|
||||
|
||||
#define ADC_CFGR_AWD1_DISABLED 0
|
||||
#define ADC_CFGR_AWD1_ALL (1 << 23)
|
||||
#define ADC_CFGR_AWD1_SINGLE(n) (((n) << 26) | (1 << 23) | (1 << 22))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CCR register configuration helpers
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CCR_DUAL_MASK (31 << 0)
|
||||
#define ADC_CCR_DUAL_FIELD(n) ((n) << 0)
|
||||
#define ADC_CCR_DELAY_MASK (15 << 8)
|
||||
#define ADC_CCR_DELAY_FIELD(n) ((n) << 8)
|
||||
#define ADC_CCR_DMACFG_MASK (1 << 13)
|
||||
#define ADC_CCR_DMACFG_ONESHOT (0 << 13)
|
||||
#define ADC_CCR_DMACFG_CIRCULAR (1 << 13)
|
||||
#define ADC_CCR_MDMA_MASK (3 << 14)
|
||||
#define ADC_CCR_MDMA_DISABLED (0 << 14)
|
||||
#define ADC_CCR_MDMA_WORD (2 << 14)
|
||||
#define ADC_CCR_MDMA_HWORD (3 << 14)
|
||||
#define ADC_CCR_CKMODE_MASK (3 << 16)
|
||||
#define ADC_CCR_CKMODE_ADCCK (0 << 16)
|
||||
#define ADC_CCR_CKMODE_AHB_DIV1 (1 << 16)
|
||||
#define ADC_CCR_CKMODE_AHB_DIV2 (2 << 16)
|
||||
#define ADC_CCR_CKMODE_AHB_DIV4 (3 << 16)
|
||||
|
||||
/* F3 headers do not define the following macros, L4 headers do.*/
|
||||
#if !defined(ADC_CCR_VREFEN) || defined(__DOXYGEN__)
|
||||
#define ADC_CCR_VREFEN (1 << 22)
|
||||
#endif
|
||||
|
||||
#if !defined(ADC_CCR_TSEN) || defined(__DOXYGEN__)
|
||||
#define ADC_CCR_TSEN (1 << 23)
|
||||
#endif
|
||||
|
||||
#if !defined(ADC_CCR_VBATEN) || defined(__DOXYGEN__)
|
||||
#define ADC_CCR_VBATEN (1 << 24)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the ADC master/slave mode.
|
||||
* @note In dual mode only ADCD1 and ADCD3 are available.
|
||||
*/
|
||||
#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_DUAL_MODE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the ADC samples type an 8bits one.
|
||||
* @note 10 and 12 bits sampling mode must not be used when this option
|
||||
* is enabled.
|
||||
*/
|
||||
#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_COMPACT_SAMPLES FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC1 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC2 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC2 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC3 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#endif
|
||||
/**
|
||||
* @brief ADC4 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC4 is included.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC4) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC4 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC4 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC4_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC4_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1/ADC2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC2 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC4 DMA interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC4_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
|
||||
#endif
|
||||
|
||||
#if defined(STM32F3XX) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC1/ADC2 clock source and mode.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC3/ADC4 clock source and mode.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#endif
|
||||
#endif /* defined(STM32F3XX) */
|
||||
|
||||
#if defined(STM32L4XX) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC1/ADC2/ADC3 clock source and mode.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC123_CLOCK_MODE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#endif
|
||||
#endif /* defined(STM32L4XX) */
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* Supported devices checks.*/
|
||||
#if !defined(STM32H7XX)
|
||||
#error "ADCv4 only supports H7 STM32 devices"
|
||||
#endif
|
||||
|
||||
/* Registry checks.*/
|
||||
#if !defined(STM32_HAS_ADC1) || !defined(STM32_HAS_ADC2) || \
|
||||
!defined(STM32_HAS_ADC3) || !defined(STM32_HAS_ADC4)
|
||||
#error "STM32_ADC_USE_ADCx not defined in registry"
|
||||
#endif
|
||||
|
||||
/* Units checks.*/
|
||||
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
|
||||
#error "ADC1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
|
||||
#error "ADC2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
|
||||
#error "ADC3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4 && !STM32_HAS_ADC4
|
||||
#error "ADC4 not present in the selected device"
|
||||
#endif
|
||||
|
||||
/* IRQ handlers checks.*/
|
||||
#if STM32_HAS_ADC1 && !defined(STM32_ADC12_HANDLER)
|
||||
#error "STM32_ADCx_HANDLER not defined in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC2 && !defined(STM32_ADC12_HANDLER)
|
||||
#error "STM32_ADCx_HANDLER not defined in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC3 && !defined(STM32_ADC34_HANDLER)
|
||||
#error "STM32_ADCx_HANDLER not defined in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC4 && !defined(STM32_ADC34_HANDLER)
|
||||
#error "STM32_ADCx_HANDLER not defined in registry"
|
||||
#endif
|
||||
|
||||
/* IRQ vector numbers checks.*/
|
||||
#if STM32_HAS_ADC1 && !defined(STM32_ADC12_NUMBER)
|
||||
#error "STM32_ADCx_NUMBER not defined in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC2 && !defined(STM32_ADC12_NUMBER)
|
||||
#error "STM32_ADCx_NUMBER not defined in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC3 && !defined(STM32_ADC34_NUMBER)
|
||||
#error "STM32_ADCx_NUMBER not defined in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_HAS_ADC4 && !defined(STM32_ADC34_NUMBER)
|
||||
#error "STM32_ADCx_NUMBER not defined in registry"
|
||||
#endif
|
||||
|
||||
/* Units checks related to dual mode.*/
|
||||
#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC1 && !STM32_HAS_ADC2
|
||||
#error "ADC2 not present in the selected device, required for dual mode"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC3 && !STM32_HAS_ADC4
|
||||
#error "ADC4 not present in the selected device, required for dual mode"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC2
|
||||
#error "ADC2 cannot be used in dual mode"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC4
|
||||
#error "ADC4 cannot be used in dual mode"
|
||||
#endif
|
||||
|
||||
/* At least one ADC must be assigned.*/
|
||||
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && \
|
||||
!STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4
|
||||
#error "ADC driver activated but no ADC peripheral assigned"
|
||||
#endif
|
||||
|
||||
/* ADC IRQ priority tests.*/
|
||||
#if STM32_ADC_USE_ADC1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC1"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC2"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC3"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC4"
|
||||
#endif
|
||||
|
||||
/* DMA IRQ priority tests.*/
|
||||
#if STM32_ADC_USE_ADC1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC1 DMA"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC2 DMA"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC3 DMA"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to ADC4 DMA"
|
||||
#endif
|
||||
|
||||
/* DMA priority tests.*/
|
||||
#if STM32_ADC_USE_ADC1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to ADC1"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to ADC2"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to ADC3"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to ADC4"
|
||||
#endif
|
||||
|
||||
/* ADC clock source checks.*/
|
||||
#if defined(STM32F3XX)
|
||||
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||
#define STM32_ADC12_CLOCK STM32_ADC12CLK
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC12_CLOCK (STM32_HCLK / 1)
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||
#define STM32_ADC12_CLOCK (STM32_HCLK / 2)
|
||||
#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||
#define STM32_ADC12_CLOCK (STM32_HCLK / 4)
|
||||
#else
|
||||
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||
#define STM32_ADC34_CLOCK STM32_ADC34CLK
|
||||
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC34_CLOCK (STM32_HCLK / 1)
|
||||
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||
#define STM32_ADC34_CLOCK (STM32_HCLK / 2)
|
||||
#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||
#define STM32_ADC34_CLOCK (STM32_HCLK / 4)
|
||||
#else
|
||||
#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX
|
||||
#error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC34_CLOCK > STM32_ADCCLK_MAX
|
||||
#error "STM32_ADC34_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
#endif /* defined(STM32F3XX) */
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
#if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
|
||||
#define STM32_ADC123_CLOCK STM32_ADC12CLK
|
||||
#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC123_CLOCK (STM32_HCLK / 1)
|
||||
#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
|
||||
#define STM32_ADC123_CLOCK (STM32_HCLK / 2)
|
||||
#elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
|
||||
#define STM32_ADC123_CLOCK (STM32_HCLK / 4)
|
||||
#else
|
||||
#error "invalid clock mode selected for STM32_ADC_ADC123_CLOCK_MODE"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC123_CLOCK > STM32_ADCCLK_MAX
|
||||
#error "STM32_ADC123_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
#endif /* defined(STM32L4XX) */
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief ADC sample data type.
|
||||
*/
|
||||
#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
|
||||
typedef uint16_t adcsample_t;
|
||||
#else
|
||||
typedef uint8_t adcsample_t;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Channels number in a conversion group.
|
||||
*/
|
||||
typedef uint16_t adc_channels_num_t;
|
||||
|
||||
/**
|
||||
* @brief Possible ADC failure causes.
|
||||
* @note Error codes are architecture dependent and should not relied
|
||||
* upon.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
|
||||
ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
|
||||
ADC_ERR_AWD1 = 2, /**< Watchdog 1 triggered. */
|
||||
ADC_ERR_AWD2 = 3, /**< Watchdog 2 triggered. */
|
||||
ADC_ERR_AWD3 = 4 /**< Watchdog 3 triggered. */
|
||||
} adcerror_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an ADC driver.
|
||||
*/
|
||||
typedef struct ADCDriver ADCDriver;
|
||||
|
||||
/**
|
||||
* @brief ADC notification callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] buffer pointer to the most recent samples data
|
||||
* @param[in] n number of buffer rows available starting from @p buffer
|
||||
*/
|
||||
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
|
||||
|
||||
/**
|
||||
* @brief ADC error callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] err ADC error code
|
||||
*/
|
||||
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
|
||||
|
||||
/**
|
||||
* @brief Conversion group configuration structure.
|
||||
* @details This implementation-dependent structure describes a conversion
|
||||
* operation.
|
||||
* @note The use of this configuration structure requires knowledge of
|
||||
* STM32 ADC cell registers interface, please refer to the STM32
|
||||
* reference manual for details.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Enables the circular buffer mode for the group.
|
||||
*/
|
||||
bool circular;
|
||||
/**
|
||||
* @brief Number of the analog channels belonging to the conversion group.
|
||||
*/
|
||||
adc_channels_num_t num_channels;
|
||||
/**
|
||||
* @brief Callback function associated to the group or @p NULL.
|
||||
*/
|
||||
adccallback_t end_cb;
|
||||
/**
|
||||
* @brief Error callback or @p NULL.
|
||||
*/
|
||||
adcerrorcallback_t error_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief ADC CFGR register initialization data.
|
||||
* @note The bits DMAEN and DMACFG are enforced internally
|
||||
* to the driver, keep them to zero.
|
||||
* @note The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
|
||||
* specified in continuous mode or if the buffer depth is
|
||||
* greater than one.
|
||||
*/
|
||||
uint32_t cfgr;
|
||||
/**
|
||||
* @brief ADC TR1 register initialization data.
|
||||
*/
|
||||
uint32_t tr1;
|
||||
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC CCR register initialization data.
|
||||
* @note The bits CKMODE, MDMA, DMACFG are enforced internally to the
|
||||
* driver, keep them to zero.
|
||||
* @note This field is only present in dual mode.
|
||||
*/
|
||||
uint32_t ccr;
|
||||
#endif
|
||||
/**
|
||||
* @brief ADC SMPRx registers initialization data.
|
||||
*/
|
||||
uint32_t smpr[2];
|
||||
/**
|
||||
* @brief ADC SQRx register initialization data.
|
||||
*/
|
||||
uint32_t sqr[4];
|
||||
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Slave ADC SMPRx registers initialization data.
|
||||
* @note This field is only present in dual mode.
|
||||
*/
|
||||
uint32_t ssmpr[2];
|
||||
/**
|
||||
* @brief Slave ADC SQRx register initialization data.
|
||||
* @note This field is only present in dual mode.
|
||||
*/
|
||||
uint32_t ssqr[4];
|
||||
#endif /* STM32_ADC_DUAL_MODE */
|
||||
} ADCConversionGroup;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief ADC DIFSEL register initialization data.
|
||||
*/
|
||||
uint32_t difsel;
|
||||
} ADCConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an ADC driver.
|
||||
*/
|
||||
struct ADCDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
adcstate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const ADCConfig *config;
|
||||
/**
|
||||
* @brief Current samples buffer pointer or @p NULL.
|
||||
*/
|
||||
adcsample_t *samples;
|
||||
/**
|
||||
* @brief Current samples buffer depth or @p 0.
|
||||
*/
|
||||
size_t depth;
|
||||
/**
|
||||
* @brief Current conversion group pointer or @p NULL.
|
||||
*/
|
||||
const ADCConversionGroup *grpp;
|
||||
#if ADC_USE_WAIT || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
thread_reference_t thread;
|
||||
#endif
|
||||
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
mutex_t mutex;
|
||||
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||||
ADC_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the master ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adcm;
|
||||
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Pointer to the slave ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adcs;
|
||||
#endif /* STM32_ADC_DUAL_MODE */
|
||||
/**
|
||||
* @brief Pointer to the common ADCx_y registers block.
|
||||
*/
|
||||
ADC_Common_TypeDef *adcc;
|
||||
/**
|
||||
* @brief Pointer to associated DMA channel.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmastp;
|
||||
/**
|
||||
* @brief DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Threashold register initializer
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sequences building helper macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Number of channels in a conversion sequence.
|
||||
*/
|
||||
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 0)
|
||||
|
||||
#define ADC_SQR1_SQ1_N(n) ((n) << 6) /**< @brief 1st channel in seq. */
|
||||
#define ADC_SQR1_SQ2_N(n) ((n) << 12) /**< @brief 2nd channel in seq. */
|
||||
#define ADC_SQR1_SQ3_N(n) ((n) << 18) /**< @brief 3rd channel in seq. */
|
||||
#define ADC_SQR1_SQ4_N(n) ((n) << 24) /**< @brief 4th channel in seq. */
|
||||
|
||||
#define ADC_SQR2_SQ5_N(n) ((n) << 0) /**< @brief 5th channel in seq. */
|
||||
#define ADC_SQR2_SQ6_N(n) ((n) << 6) /**< @brief 6th channel in seq. */
|
||||
#define ADC_SQR2_SQ7_N(n) ((n) << 12) /**< @brief 7th channel in seq. */
|
||||
#define ADC_SQR2_SQ8_N(n) ((n) << 18) /**< @brief 8th channel in seq. */
|
||||
#define ADC_SQR2_SQ9_N(n) ((n) << 24) /**< @brief 9th channel in seq. */
|
||||
|
||||
#define ADC_SQR3_SQ10_N(n) ((n) << 0) /**< @brief 10th channel in seq.*/
|
||||
#define ADC_SQR3_SQ11_N(n) ((n) << 6) /**< @brief 11th channel in seq.*/
|
||||
#define ADC_SQR3_SQ12_N(n) ((n) << 12) /**< @brief 12th channel in seq.*/
|
||||
#define ADC_SQR3_SQ13_N(n) ((n) << 18) /**< @brief 13th channel in seq.*/
|
||||
#define ADC_SQR3_SQ14_N(n) ((n) << 24) /**< @brief 14th channel in seq.*/
|
||||
|
||||
#define ADC_SQR4_SQ15_N(n) ((n) << 0) /**< @brief 15th channel in seq.*/
|
||||
#define ADC_SQR4_SQ16_N(n) ((n) << 6) /**< @brief 16th channel in seq.*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rate settings helper macros
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SMPR1_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
|
||||
|
||||
#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN16(n) ((n) << 18) /**< @brief AN16 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN17(n) ((n) << 21) /**< @brief AN17 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD2;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD3;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD4;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void adc_lld_init(void);
|
||||
void adc_lld_start(ADCDriver *adcp);
|
||||
void adc_lld_stop(ADCDriver *adcp);
|
||||
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||
void adcSTM32EnableVREF(ADCDriver *adcp);
|
||||
void adcSTM32DisableVREF(ADCDriver *adcp);
|
||||
void adcSTM32EnableTS(ADCDriver *adcp);
|
||||
void adcSTM32DisableTS(ADCDriver *adcp);
|
||||
void adcSTM32EnableVBAT(ADCDriver *adcp);
|
||||
void adcSTM32DisableVBAT(ADCDriver *adcp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
#endif /* HAL_ADC_LLD_H */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,13 @@
|
|||
STM32 ADCv4 driver.
|
||||
|
||||
Driver capability:
|
||||
|
||||
- Supports the STM32 "fast" ADC found on H7 sub-family.
|
||||
|
||||
The file registry must export:
|
||||
|
||||
STM32_HAS_ADCx - ADCx presence flag (1..4).
|
||||
STM32_ADC12_HANDLER - IRQ vector name for ADC1 and ADC2.
|
||||
STM32_ADC12_NUMBER - IRQ vector number for ADC1 and ADC2.
|
||||
STM32_ADC34_HANDLER - IRQ vector name for ADC3 and ADC4.
|
||||
STM32_ADC34_NUMBER - IRQ vector number for ADC3 and ADC4.
|
|
@ -21,12 +21,12 @@ else
|
|||
endif
|
||||
|
||||
# Drivers compatible with the platform.
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv4/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/BDMAv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
|
||||
|
|
|
@ -38,11 +38,12 @@
|
|||
/*===========================================================================*/
|
||||
#if defined(STM32H743xx) || defined(STM32H753xx) || \
|
||||
defined(__DOXYGEN__)
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC12_HANDLER Vector88
|
||||
#define STM32_ADC12_NUMBER 18
|
||||
#define STM32_ADC3_HANDLER Vector23C
|
||||
#define STM32_ADC3_NUMBER 127
|
||||
#define STM32_ADC34_HANDLER Vector23C
|
||||
#define STM32_ADC34_NUMBER 127
|
||||
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
|
||||
|
|
Loading…
Reference in New Issue