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Fixed bug #768. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9732 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2016-08-02 08:27:44 +00:00
parent af8eecac13
commit 85c2cac71d
3 changed files with 97 additions and 38 deletions
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36
os/hal/ports/STM32/STM32L4xx/hal_lld.c
View File

@ -48,7 +48,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/** /**
* @brief Initializes the backup domain. * @brief Initializes the backup domain.
* @note WARNING! Changing clock source impossible without resetting * @note WARNING! Changing RTC clock source impossible without resetting
* of the whole BKP domain. * of the whole BKP domain.
*/ */
static void hal_lld_backup_domain_init(void) { static void hal_lld_backup_domain_init(void) {
@ -218,12 +218,11 @@ void stm32_clock_init(void) {
; /* Wait until LSE is stable. */ ; /* Wait until LSE is stable. */
#endif #endif
#if STM32_MSIPLL_ENABLED /* Flash setup for selected MSI speed setting.*/
/* MSI PLL activation.*/ FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
RCC->CR |= RCC_CR_MSIPLLEN; STM32_MSI_FLASHBITS;
#endif
/* Changing MSIRANGE value. Meanwhile range is set by MSISRANGE which is 4MHz.*/ /* Changing MSIRANGE to configured value.*/
RCC->CR |= STM32_MSIRANGE; RCC->CR |= STM32_MSIRANGE;
/* Switching from MSISRANGE to MSIRANGE.*/ /* Switching from MSISRANGE to MSIRANGE.*/
@ -231,6 +230,15 @@ void stm32_clock_init(void) {
while ((RCC->CR & RCC_CR_MSIRDY) == 0) while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; ;
/* MSI is configured SYSCLK source so wait for it to be stable as well.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
;
#if STM32_MSIPLL_ENABLED
/* MSI PLL (to LSE) activation */
RCC->CR |= RCC_CR_MSIPLLEN;
#endif
/* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high. /* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high.
This range is used exiting the Standby mode until MSIRGSEL is set.*/ This range is used exiting the Standby mode until MSIRGSEL is set.*/
RCC->CSR |= STM32_MSISRANGE; RCC->CSR |= STM32_MSISRANGE;
@ -251,7 +259,7 @@ void stm32_clock_init(void) {
/* Waiting for PLL lock.*/ /* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLRDY) == 0) while ((RCC->CR & RCC_CR_PLLRDY) == 0)
; ;
#endif /* STM32_OVERDRIVE_REQUIRED */ #endif
#if STM32_ACTIVATE_PLLSAI1 #if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/ /* PLLSAI1 activation.*/
@ -299,16 +307,22 @@ void stm32_clock_init(void) {
RCC->CCIPR = ccipr; RCC->CCIPR = ccipr;
} }
/* Flash setup.*/ /* Set flash WS's for SYSCLK source */
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)
STM32_FLASHBITS; FLASH->ACR = STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from MSI.*/ /* Switching to the configured SYSCLK source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI) #if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
/* Wait until SYSCLK is stable.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
; ;
#endif #endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)
FLASH->ACR = STM32_FLASHBITS;
#endif /* STM32_NO_INIT */ #endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared /* SYSCFG clock enabled here because it is a multi-functional unit shared

93
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -34,8 +34,8 @@
* @{ * @{
*/ */
#ifndef _HAL_LLD_H_ #ifndef HAL_LLD_H
#define _HAL_LLD_H_ #define HAL_LLD_H
#include "stm32_registry.h" #include "stm32_registry.h"
@ -1137,6 +1137,9 @@
#elif STM32_PLLSRC == STM32_PLLSRC_HSI16 #elif STM32_PLLSRC == STM32_PLLSRC_HSI16
#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE) #define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLCLKIN 0
#else #else
#error "invalid STM32_PLLSRC value specified" #error "invalid STM32_PLLSRC value specified"
#endif #endif
@ -1144,7 +1147,8 @@
/* /*
* PLLs input frequency range check. * PLLs input frequency range check.
*/ */
#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) #if (STM32_PLLCLKIN != 0) && \
((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" #error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif #endif
@ -1157,6 +1161,11 @@
(STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \ (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \ (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
defined(__DOXYGEN__) defined(__DOXYGEN__)
#if STM32_PLLCLKIN == 0
#error "PLL activation required but no PLL clock selected"
#endif
/** /**
* @brief PLL activation flag. * @brief PLL activation flag.
*/ */
@ -1265,7 +1274,8 @@
/* /*
* PLL VCO frequency range check. * PLL VCO frequency range check.
*/ */
#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) #if STM32_ACTIVATE_PLL && \
((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif #endif
@ -1287,21 +1297,24 @@
/* /*
* PLL-P output frequency range check. * PLL-P output frequency range check.
*/ */
#if (STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX) #if STM32_ACTIVATE_PLL && \
((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" #error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif #endif
/* /*
* PLL-Q output frequency range check. * PLL-Q output frequency range check.
*/ */
#if (STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX) #if STM32_ACTIVATE_PLL && \
((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" #error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif #endif
/* /*
* PLL-R output frequency range check. * PLL-R output frequency range check.
*/ */
#if (STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX) #if STM32_ACTIVATE_PLL && \
((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" #error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif #endif
@ -1439,6 +1452,11 @@
(STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \ (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \ (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
defined(__DOXYGEN__) defined(__DOXYGEN__)
#if STM32_PLLCLKIN == 0
#error "PLLSAI1 activation required but no PLL clock selected"
#endif
/** /**
* @brief PLLSAI1 activation flag. * @brief PLLSAI1 activation flag.
*/ */
@ -1543,11 +1561,11 @@
#define STM32_PLLSAI1VCO (STM32_PLLCLKIN * STM32_PLLSAI1N_VALUE) #define STM32_PLLSAI1VCO (STM32_PLLCLKIN * STM32_PLLSAI1N_VALUE)
/* /*
* PLLSAI2 VCO frequency range check. * PLLSAI1 VCO frequency range check.
*/ */
#if (STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || \ #if STM32_ACTIVATE_PLLSAI1 && \
(STM32_PLLSAI1VCO > STM32_PLLVCO_MAX) ((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX))
#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif #endif
/** /**
@ -1568,24 +1586,24 @@
/* /*
* PLLSAI1-P output frequency range check. * PLLSAI1-P output frequency range check.
*/ */
#if (STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || \ #if STM32_ACTIVATE_PLLSAI1 && \
(STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX) ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" #error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif #endif
/* /*
* PLLSAI1-Q output frequency range check. * PLLSAI1-Q output frequency range check.
*/ */
#if (STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || \ #if STM32_ACTIVATE_PLLSAI1 && \
(STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX) ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)" #error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif #endif
/* /*
* PLLSAI1-R output frequency range check. * PLLSAI1-R output frequency range check.
*/ */
#if (STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || \ #if STM32_ACTIVATE_PLLSAI1 && \
(STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX) ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" #error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif #endif
@ -1596,6 +1614,11 @@
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || \ (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || \
defined(__DOXYGEN__) defined(__DOXYGEN__)
#if STM32_PLLCLKIN == 0
#error "PLLSAI2 activation required but no PLL clock selected"
#endif
/** /**
* @brief PLLSAI2 activation flag. * @brief PLLSAI2 activation flag.
*/ */
@ -1674,9 +1697,9 @@
/* /*
* PLLSAI2 VCO frequency range check. * PLLSAI2 VCO frequency range check.
*/ */
#if (STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || \ #if STM32_ACTIVATE_PLLSAI2 && \
(STM32_PLLSAI2VCO > STM32_PLLVCO_MAX) ((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX))
#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif #endif
/** /**
@ -1692,16 +1715,16 @@
/* /*
* PLLSAI2-P output frequency range check. * PLLSAI2-P output frequency range check.
*/ */
#if (STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || \ #if STM32_ACTIVATE_PLLSAI2 && \
(STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX) ((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)" #error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif #endif
/* /*
* PLLSAI2-R output frequency range check. * PLLSAI2-R output frequency range check.
*/ */
#if (STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || \ #if STM32_ACTIVATE_PLLSAI2 && \
(STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX) ((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)" #error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif #endif
@ -2030,6 +2053,26 @@
#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS #define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
#endif #endif
/**
* @brief Flash settings for MSI.
*/
#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS
#elif STM32_MSICLK <= STM32_1WS_THRESHOLD
#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS
#elif STM32_MSICLK <= STM32_2WS_THRESHOLD
#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS
#elif STM32_MSICLK <= STM32_3WS_THRESHOLD
#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS
#else
#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/
@ -2056,6 +2099,6 @@ extern "C" {
} }
#endif #endif
#endif /* _HAL_LLD_H_ */ #endif /* HAL_LLD_H */
/** @} */ /** @} */

2
readme.txt
View File

@ -73,6 +73,8 @@
***************************************************************************** *****************************************************************************
*** 16.1.6 *** *** 16.1.6 ***
- HAL: Fixed potential wait states problem in STM32L4 initialization code
(bug #768).
- HAL: Fixed SDIO driver not compiling on STM32F446 devices (bug #767). - HAL: Fixed SDIO driver not compiling on STM32F446 devices (bug #767).
- HAL: Fixed error in STM32L4xx ST headers (bug #766). - HAL: Fixed error in STM32L4xx ST headers (bug #766).
- HAL: Fixed wrong check in win32 simulator serial driver (bug #765). - HAL: Fixed wrong check in win32 simulator serial driver (bug #765).