diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc
index 1b4bf5267..46ad4adc3 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc
@@ -30,8 +30,8 @@
  * @name    HPRE field bits definitions
  * @{
  */
-#define STM32_HPRE_MASK         (15U << 4U) /**< HPRE field mask.           */
-#define STM32_HPRE_FIELD(n)     ((n) << 4U) /**< HPRE field value.          */
+#define STM32_HPRE_MASK         (15U << RCC_CFGR_HPRE_Pos)
+#define STM32_HPRE_FIELD(n)     ((n) << RCC_CFGR_HPRE_Pos)
 #define STM32_HPRE_DIV1         STM32_HPRE_FIELD(0U)
 #define STM32_HPRE_DIV2         STM32_HPRE_FIELD(8U)
 #define STM32_HPRE_DIV4         STM32_HPRE_FIELD(9U)
@@ -67,31 +67,31 @@
  * @brief   AHB frequency.
  */
 #if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#define STM32_HCLK                  (STM32_SYSCLK / 1U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#define STM32_HCLK                  (STM32_SYSCLK / 2U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#define STM32_HCLK                  (STM32_SYSCLK / 4U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#define STM32_HCLK                  (STM32_SYSCLK / 8U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#define STM32_HCLK                  (STM32_SYSCLK / 16U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#define STM32_HCLK                  (STM32_SYSCLK / 64U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#define STM32_HCLK                  (STM32_SYSCLK / 128U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#define STM32_HCLK                  (STM32_SYSCLK / 256U)
 
 #elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#define STM32_HCLK                  (STM32_SYSCLK / 512U)
 
 #else
 #error "invalid STM32_HPRE value specified"
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc
index 56ce72b3b..a23c2845f 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc
@@ -30,8 +30,8 @@
  * @name    PPRE1 field bits definitions
  * @{
  */
-#define STM32_PPRE1_MASK        (7U << 8U)   /**< PPRE1 field mask.         */
-#define STM32_PPRE1_FIELD(n)    ((n) << 8U)  /**< PPRE1 field value.        */
+#define STM32_PPRE1_MASK        (7U << RCC_CFGR_PPRE1_Pos)
+#define STM32_PPRE1_FIELD(n)    ((n) << RCC_CFGR_PPRE1_Pos)
 #define STM32_PPRE1_DIV1        STM32_PPRE1_FIELD(0U)
 #define STM32_PPRE1_DIV2        STM32_PPRE1_FIELD(4U)
 #define STM32_PPRE1_DIV4        STM32_PPRE1_FIELD(5U)
@@ -63,19 +63,19 @@
  * @brief   APB1 frequency.
  */
 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
+#define STM32_PCLK1                 (STM32_HCLK / 1U)
 
 #elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
+#define STM32_PCLK1                 (STM32_HCLK / 2U)
 
 #elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
+#define STM32_PCLK1                 (STM32_HCLK / 4U)
 
 #elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
+#define STM32_PCLK1                 (STM32_HCLK / 8U)
 
 #elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
+#define STM32_PCLK1                 (STM32_HCLK / 16U)
 
 #else
 #error "invalid STM32_PPRE1 value specified"
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc
index 97e58b833..eeb96e1e2 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc
@@ -30,8 +30,8 @@
  * @name    PPRE1 field bits definitions
  * @{
  */
-#define STM32_PPRE2_MASK        (7U << 11U)  /**< PPRE2 field mask.         */
-#define STM32_PPRE2_FIELD(n)    ((n) << 11U) /**< PPRE2 field value.        */
+#define STM32_PPRE2_MASK        (7U << RCC_CFGR_PPRE2_Pos)
+#define STM32_PPRE2_FIELD(n)    ((n) << RCC_CFGR_PPRE2_Pos)
 #define STM32_PPRE2_DIV1        STM32_PPRE2_FIELD(0U)
 #define STM32_PPRE2_DIV2        STM32_PPRE2_FIELD(4U)
 #define STM32_PPRE2_DIV4        STM32_PPRE2_FIELD(5U)
@@ -63,19 +63,19 @@
  * @brief   APB2 frequency.
  */
 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
+#define STM32_PCLK2                 (STM32_HCLK / 1U)
 
 #elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
+#define STM32_PCLK2                 (STM32_HCLK / 2U)
 
 #elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
+#define STM32_PCLK2                 (STM32_HCLK / 4U)
 
 #elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
+#define STM32_PCLK2                 (STM32_HCLK / 8U)
 
 #elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
+#define STM32_PCLK2                 (STM32_HCLK / 16U)
 
 #else
 #error "invalid STM32_PPRE2 value specified"
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
index 12f69f04e..301151fa1 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
@@ -99,7 +99,7 @@ static inline void hse_init(void) {
 #endif
   /* HSE activation.*/
   RCC->CR |= RCC_CR_HSEON;
-  while ((RCC->CR & RCC_CR_HSERDY) == 0) {
+  while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
   }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
index 1538b3305..9f1bec281 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
@@ -29,7 +29,7 @@
 /**
  * @brief   HSI16 clock frequency.
  */
-#define STM32_HSI16CLK          16000000
+#define STM32_HSI16CLK          16000000U
 
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
@@ -62,7 +62,7 @@ static inline void hsi16_init(void) {
 #if STM32_HSI16_ENABLED
   /* HSI activation.*/
   RCC->CR |= RCC_CR_HSION;
-  while ((RCC->CR & RCC_CR_HSIRDY) == 0) {
+  while ((RCC->CR & RCC_CR_HSIRDY) == 0U) {
   }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
index dc60a2fe1..ec4dbb2dc 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc
@@ -29,7 +29,7 @@
 /**
  * @brief   HSI48 clock frequency.
  */
-#define STM32_HSI48CLK          48000000
+#define STM32_HSI48CLK          48000000U
 
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
@@ -66,7 +66,7 @@ static inline void hsi48_init(void) {
 #if STM32_HSI48_ENABLED
   /* HSI activation.*/
   RCC->CRRCR |= RCC_CRRCR_HSI48ON;
-  while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0) {
+  while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0U) {
   }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc
index a4c6167ce..4741ac6ce 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc
@@ -29,15 +29,15 @@
 /**
  * @brief   LSI clock frequency.
  */
-#define STM32_LSIRCCLK          32000
+#define STM32_LSIRCCLK          32000U
 
 /**
  * @name    RCC_CSR register bits definitions
  * @{
  */
-#define STM32_LSIPRE_MASK       (1 << 4)    /**< LSIPRE field mask.         */
-#define STM32_LSIPRE_NODIV      (0 << 4)    /**< LSI not divided.           */
-#define STM32_LSIPRE_DIV128     (1 << 4)    /**< LSI divided by 128         */
+#define STM32_LSIPRE_MASK       (1U << RCC_CSR_LSIPRE_Pos)
+#define STM32_LSIPRE_NODIV      (0U << RCC_CSR_LSIPRE_Pos)
+#define STM32_LSIPRE_DIV128     (1U << RCC_CSR_LSIPRE_Pos)
 /** @} */
 
 /*===========================================================================*/
@@ -70,13 +70,13 @@
 #if (STM32_LSIPRE == STM32_LSIPRE_NODIV) || defined(__DOXYGEN__)
 #define STM32_LSICLK                (STM32_LSIRCCLK)
 #elif STM32_LSIPRE == STM32_LSIPRE_DIV128
-#define STM32_LSICLK                (STM32_LSIRCCLK / 128)
+#define STM32_LSICLK                (STM32_LSIRCCLK / 128U)
 #else
 #error "invalid STM32_LSIPRE value specified"
 #endif
 
 #else /* !STM32_RCC_HAS_LSI_PRESCALER */
-#define STM32_LSIPRE                0
+#define STM32_LSIPRE                0U
 #define STM32_LSICLK                (STM32_LSIRCCLK)
 #endif /* !STM32_RCC_HAS_LSI_PRESCALER */
 
@@ -97,7 +97,7 @@ static inline void lsi_init(void) {
 #if STM32_LSI_ENABLED
   /* LSI activation.*/
   RCC->CSR |= STM32_LSIPRE | RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) {
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0U) {
   }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
index b7492e97f..f987314a2 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
@@ -30,30 +30,30 @@
  * @name    RCC_CR register bits definitions
  * @{
  */
-#define STM32_MSIRANGE_MASK     (15 << 4)   /**< MSIRANGE field mask.       */
-#define STM32_MSIRANGE_100K     (0 << 4)    /**< 100kHz nominal.            */
-#define STM32_MSIRANGE_200K     (1 << 4)    /**< 200kHz nominal.            */
-#define STM32_MSIRANGE_400K     (2 << 4)    /**< 400kHz nominal.            */
-#define STM32_MSIRANGE_800K     (3 << 4)    /**< 800kHz nominal.            */
-#define STM32_MSIRANGE_1M       (4 << 4)    /**< 1MHz nominal.              */
-#define STM32_MSIRANGE_2M       (5 << 4)    /**< 2MHz nominal.              */
-#define STM32_MSIRANGE_4M       (6 << 4)    /**< 4MHz nominal.              */
-#define STM32_MSIRANGE_8M       (7 << 4)    /**< 8MHz nominal.              */
-#define STM32_MSIRANGE_16M      (8 << 4)    /**< 16MHz nominal.             */
-#define STM32_MSIRANGE_24M      (9 << 4)    /**< 24MHz nominal.             */
-#define STM32_MSIRANGE_32M      (10 << 4)   /**< 32MHz nominal.             */
-#define STM32_MSIRANGE_48M      (11 << 4)   /**< 48MHz nominal.             */
+#define STM32_MSIRANGE_MASK     (15U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_100K     (0U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_200K     (1U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_400K     (2U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_800K     (3U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_1M       (4U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_2M       (5U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_4M       (6U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_8M       (7U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_16M      (8U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_24M      (9U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_32M      (10U << RCC_CR_MSIRANGE_Pos)
+#define STM32_MSIRANGE_48M      (11U << RCC_CR_MSIRANGE_Pos)
 /** @} */
 
 /**
  * @name    RCC_CSR register bits definitions
  * @{
  */
-#define STM32_MSISRANGE_MASK    (15 << 8)   /**< MSISRANGE field mask.      */
-#define STM32_MSISRANGE_1M      (4 << 8)    /**< 1MHz nominal.              */
-#define STM32_MSISRANGE_2M      (5 << 8)    /**< 2MHz nominal.              */
-#define STM32_MSISRANGE_4M      (6 << 8)    /**< 4MHz nominal.              */
-#define STM32_MSISRANGE_8M      (7 << 8)    /**< 8MHz nominal.              */
+#define STM32_MSISRANGE_MASK    (15U << RCC_CSR_MSISRANGE_Pos)
+#define STM32_MSISRANGE_1M      (4U << RCC_CSR_MSISRANGE_Pos)
+#define STM32_MSISRANGE_2M      (5U << RCC_CSR_MSISRANGE_Pos)
+#define STM32_MSISRANGE_4M      (6U << RCC_CSR_MSISRANGE_Pos)
+#define STM32_MSISRANGE_8M      (7U << RCC_CSR_MSISRANGE_Pos)
 /** @} */
 
 /*===========================================================================*/
@@ -90,29 +90,41 @@
  * @brief   MSI frequency.
  */
 #if STM32_MSIRANGE == STM32_MSIRANGE_100K
-  #define STM32_MSICLK              100000
+  #define STM32_MSICLK              100000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_200K
-  #define STM32_MSICLK              200000
+  #define STM32_MSICLK              200000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_400K
-  #define STM32_MSICLK              400000
+  #define STM32_MSICLK              400000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_800K
-  #define STM32_MSICLK              800000
+  #define STM32_MSICLK              800000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_1M
-  #define STM32_MSICLK              1000000
+  #define STM32_MSICLK              1000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_2M
-  #define STM32_MSICLK              2000000
+  #define STM32_MSICLK              2000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_4M
-  #define STM32_MSICLK              4000000
+  #define STM32_MSICLK              4000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_8M
-  #define STM32_MSICLK              8000000
+  #define STM32_MSICLK              8000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_16M
-  #define STM32_MSICLK              16000000
+  #define STM32_MSICLK              16000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_24M
-  #define STM32_MSICLK              24000000
+  #define STM32_MSICLK              24000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_32M
-  #define STM32_MSICLK              32000000
+  #define STM32_MSICLK              32000000U
+
 #elif STM32_MSIRANGE == STM32_MSIRANGE_48M
-  #define STM32_MSICLK              48000000
+  #define STM32_MSICLK              48000000U
+
 #else
   #error "invalid STM32_MSIRANGE value specified"
 #endif
@@ -121,13 +133,17 @@
  * @brief   MSIS frequency.
  */
 #if STM32_MSISRANGE == STM32_MSISRANGE_1M
-  #define STM32_MSISCLK             1000000
+  #define STM32_MSISCLK             1000000U
+
 #elif STM32_MSISRANGE == STM32_MSISRANGE_2M
-  #define STM32_MSISCLK             2000000
+  #define STM32_MSISCLK             2000000U
+
 #elif STM32_MSISRANGE == STM32_MSISRANGE_4M
-  #define STM32_MSISCLK             4000000
+  #define STM32_MSISCLK             4000000U
+
 #elif STM32_MSISRANGE == STM32_MSISRANGE_8M
-  #define STM32_MSISCLK             8000000
+  #define STM32_MSISCLK             8000000U
+
 #else
   #error "invalid STM32_MSISRANGE value specified"
 #endif
@@ -149,12 +165,12 @@ static inline void msi_reset(void) {
   /* Resetting to the MSI clock in case we come here after an initialization,
      because a debugger for example.*/
   RCC->CR = RCC_CR_MSION;
-  while ((RCC->CR & RCC_CR_MSIRDY) == 0) {
+  while ((RCC->CR & RCC_CR_MSIRDY) == 0U) {
     /* Wait until MSI is stable.*/
   }
 
   /* Clocking from MSI, in case MSI was not the default source.*/
-  RCC->CFGR = 0;
+  RCC->CFGR = 0U;
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) {
     /* Wait until MSI is selected.*/
   }
@@ -175,12 +191,12 @@ static inline void msi_init(void) {
   cr = STM32_MSIRANGE | RCC_CR_MSION;
 #endif
   RCC->CR = cr;
-  while ((RCC->CR & RCC_CR_MSIRDY) == 0) {
+  while ((RCC->CR & RCC_CR_MSIRDY) == 0U) {
     /* Wait until MSI is stable.*/
   }
 
   /* Clocking from MSI, in case MSI was not the default source.*/
-  RCC->CFGR = 0;
+  RCC->CFGR = 0U;
   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
     ;                                       /* Wait until MSI is selected.  */
 
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
index 19e0f0269..5494f7bfa 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
@@ -138,7 +138,7 @@
  */
 #if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) ||                \
     defined(__DOXYGEN__)
-#define STM32_PLLM                  ((STM32_PLLM_VALUE - 1) << 4)
+#define STM32_PLLM                  ((STM32_PLLM_VALUE - 1U) << RCC_PLLCFGR_PLLM_Pos)
 
 #else
 #error "invalid STM32_PLLM_VALUE value specified"
@@ -149,7 +149,7 @@
  */
 #if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) ||               \
     defined(__DOXYGEN__)
-#define STM32_PLLN                  (STM32_PLLN_VALUE << 8)
+#define STM32_PLLN                  (STM32_PLLN_VALUE << RCC_PLLCFGR_PLLN_Pos)
 
 #else
 #error "invalid STM32_PLLN_VALUE value specified"
@@ -176,23 +176,24 @@
  * @brief   STM32_PLLP field.
  */
 #if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
-#define STM32_PLLP                  (0 << 17)
+#define STM32_PLLP                  (0U << RCC_PLLCFGR_PLLP_Pos)
 
 #elif STM32_PLLP_VALUE == 17
-#define STM32_PLLP                  (1 << 17)
+#define STM32_PLLP                  (1U << RCC_PLLCFGR_PLLP_Pos)
 
 #else
 #error "invalid STM32_PLLP_VALUE value specified"
 #endif
 
+/* PDIV is not present on all devices.*/
+#if defined(RCC_PLLCFGR_PLLPDIV_Pos) || defined(__DOXYGEN__)
 /**
  * @brief   STM32_PLLPDIV field.
  */
 #if (STM32_PLLPDIV_VALUE == 0) ||                                           \
     ((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) ||          \
     defined(__DOXYGEN__)
-#define STM32_PLLPDIV               (STM32_PLLPDIV_VALUE << 27)
-
+#define STM32_PLLPDIV               (STM32_PLLPDIV_VALUE << RCC_PLLCFGR_PLLPDIV_Pos)
 #else
 #error "invalid STM32_PLLPDIV_VALUE value specified"
 #endif
@@ -206,6 +207,11 @@
 #define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
 #endif
 
+#else
+#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLP_VALUE)
+#define STM32_PLLPDIV               0U
+#endif
+
 /*
  * PLL-P output frequency range check.
  */
@@ -215,8 +221,8 @@
 #endif
 
 #else /* !STM32_RCC_PLL_HAS_P */
-#define STM32_PLLP                  0
-#define STM32_PLLPEN                0
+#define STM32_PLLP                  0U
+#define STM32_PLLPEN                0U
 #endif /* !STM32_RCC_PLL_HAS_P */
 
 /*---------------------------------------------------------------------------*/
@@ -227,16 +233,16 @@
  * @brief   STM32_PLLQ field.
  */
 #if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLQ                  (0 << 21)
+#define STM32_PLLQ                  (0U << RCC_PLLCFGR_PLLQ_Pos)
 
 #elif STM32_PLLQ_VALUE == 4
-#define STM32_PLLQ                  (1 << 21)
+#define STM32_PLLQ                  (1U << RCC_PLLCFGR_PLLQ_Pos)
 
 #elif STM32_PLLQ_VALUE == 6
-#define STM32_PLLQ                  (2 << 21)
+#define STM32_PLLQ                  (2U << RCC_PLLCFGR_PLLQ_Pos)
 
 #elif STM32_PLLQ_VALUE == 8
-#define STM32_PLLQ                  (3 << 21)
+#define STM32_PLLQ                  (3U << RCC_PLLCFGR_PLLQ_Pos)
 
 #else
 #error "invalid STM32_PLLQ_VALUE value specified"
@@ -256,8 +262,8 @@
 #endif
 
 #else /* !STM32_RCC_PLL_HAS_Q */
-#define STM32_PLLQ                  0
-#define STM32_PLLQEN                0
+#define STM32_PLLQ                  0U
+#define STM32_PLLQEN                0U
 #endif /* !STM32_RCC_PLL_HAS_Q */
 
 /*---------------------------------------------------------------------------*/
@@ -268,16 +274,16 @@
  * @brief   STM32_PLLR field.
  */
 #if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLR                  (0 << 25)
+#define STM32_PLLR                  (0U << RCC_PLLCFGR_PLLR_Pos)
 
 #elif STM32_PLLR_VALUE == 4
-#define STM32_PLLR                  (1 << 25)
+#define STM32_PLLR                  (1U << RCC_PLLCFGR_PLLR_Pos)
 
 #elif STM32_PLLR_VALUE == 6
-#define STM32_PLLR                  (2 << 25)
+#define STM32_PLLR                  (2U << RCC_PLLCFGR_PLLR_Pos)
 
 #elif STM32_PLLR_VALUE == 8
-#define STM32_PLLR                  (3 << 25)
+#define STM32_PLLR                  (3U << RCC_PLLCFGR_PLLR_Pos)
 
 #else
 #error "invalid STM32_PLLR_VALUE value specified"
@@ -297,8 +303,8 @@
 #endif
 
 #else /* !STM32_RCC_PLL_HAS_R */
-#define STM32_PLLR                  0
-#define STM32_PLLREN                0
+#define STM32_PLLR                  0U
+#define STM32_PLLREN                0U
 #endif /* !STM32_RCC_PLL_HAS_R */
 
 /*===========================================================================*/
@@ -325,15 +331,17 @@ static inline void pll_init(void) {
   RCC->CR |= RCC_CR_PLLON;
 
   /* Waiting for PLL lock.*/
-  while ((RCC->CR & RCC_CR_PLLRDY) == 0)
+  while ((RCC->CR & RCC_CR_PLLRDY) == 0U)
     ;
 #endif
 }
 
 static inline void pll_deinit(void) {
 
+#if STM32_ACTIVATE_PLL
   /* PLL de-activation.*/
   RCC->PLLCFGR &= ~RCC_CR_PLLON;
+#endif
 }
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
index fd40314a5..31d4ef202 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
@@ -26,6 +26,11 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+/* Required for compatibility with those devices with a common M divider.*/
+#if !defined(RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
+#define RCC_PLLSAI1CFGR_PLLSAI1M_Pos    RCC_PLLCFGR_PLLM_Pos
+#endif
+
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
@@ -138,7 +143,7 @@
  */
 #if ((STM32_PLLSAI1M_VALUE >= 1) && (STM32_PLLSAI1M_VALUE <= 16)) ||        \
     defined(__DOXYGEN__)
-#define STM32_PLLSAI1M              ((STM32_PLLSAI1M_VALUE - 1) << 4)
+#define STM32_PLLSAI1M              ((STM32_PLLSAI1M_VALUE - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
 
 #else
 #error "invalid STM32_PLLSAI1M_VALUE value specified"
@@ -149,7 +154,7 @@
  */
 #if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 127)) ||       \
     defined(__DOXYGEN__)
-#define STM32_PLLSAI1N              (STM32_PLLSAI1N_VALUE << 8)
+#define STM32_PLLSAI1N              (STM32_PLLSAI1N_VALUE << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
 
 #else
 #error "invalid STM32_PLLSAI1N_VALUE value specified"
@@ -176,21 +181,23 @@
  * @brief   STM32_PLLSAI1P field.
  */
 #if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1P              (0 << 17)
+#define STM32_PLLSAI1P              (0U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
 
 #elif STM32_PLLSAI1P_VALUE == 17
-#define STM32_PLLSAI1P              (1 << 17)
+#define STM32_PLLSAI1P              (1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
 
 #else
 #error "invalid STM32_PLLSAI1P_VALUE value specified"
 #endif
 
+/* SAI1PDIV is not present on all devices.*/
+#if defined(RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) || defined(__DOXYGEN__)
 /**
  * @brief   STM32_PLLSAI1PDIV field.
  */
 #if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) ||  \
     defined(__DOXYGEN__)
-#define STM32_PLLSAI1PDIV           (STM32_PLLSAI1PDIV_VALUE << 27)
+#define STM32_PLLSAI1PDIV           (STM32_PLLSAI1PDIV_VALUE << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
 #else
 #error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
 #endif
@@ -204,17 +211,22 @@
 #define STM32_PLLSAI1_P_CLKOUT      (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
 #endif
 
+#else
+#define STM32_PLLSAI1PDIV           0U
+#define STM32_PLLSAI1_P_CLKOUT      (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
+#endif
+
 /*
  * PLLSAI1-P output frequency range check.
  */
-#if STM32_ACTIVATE_PLLSAI1 &&                                                   \
+#if STM32_ACTIVATE_PLLSAI1 &&                                               \
     ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
 #error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
 #endif
 
 #else /* !STM32_RCC_PLLSAI1_HAS_P */
-#define STM32_PLLSAI1P              0
-#define STM32_PLLSAI1PEN            0
+#define STM32_PLLSAI1P              0U
+#define STM32_PLLSAI1PEN            0U
 #endif /* !STM32_RCC_PLLSAI1_HAS_P */
 
 /*---------------------------------------------------------------------------*/
@@ -225,16 +237,16 @@
  * @brief   STM32_PLLSAI1Q field.
  */
 #if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1Q              (0 << 21)
+#define STM32_PLLSAI1Q              (0U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
 
 #elif STM32_PLLSAI1Q_VALUE == 4
-#define STM32_PLLSAI1Q              (1 << 21)
+#define STM32_PLLSAI1Q              (1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
 
 #elif STM32_PLLSAI1Q_VALUE == 6
-#define STM32_PLLSAI1Q              (2 << 21)
+#define STM32_PLLSAI1Q              (2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
 
 #elif STM32_PLLSAI1Q_VALUE == 8
-#define STM32_PLLSAI1Q              (3 << 21)
+#define STM32_PLLSAI1Q              (3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
 
 #else
 #error "invalid STM32_PLLSAI1Q_VALUE value specified"
@@ -254,8 +266,8 @@
 #endif
 
 #else /* !STM32_RCC_PLLSAI1_HAS_Q */
-#define STM32_PLLSAI1Q              0
-#define STM32_PLLSAI1QEN            0
+#define STM32_PLLSAI1Q              0U
+#define STM32_PLLSAI1QEN            0U
 #endif /* !STM32_RCC_PLLSAI1_HAS_Q */
 
 /*---------------------------------------------------------------------------*/
@@ -266,16 +278,16 @@
  * @brief   STM32_PLLSAI1R field.
  */
 #if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1R              (0 << 25)
+#define STM32_PLLSAI1R              (0U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
 
 #elif STM32_PLLSAI1R_VALUE == 4
-#define STM32_PLLSAI1R              (1 << 25)
+#define STM32_PLLSAI1R              (1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
 
 #elif STM32_PLLSAI1R_VALUE == 6
-#define STM32_PLLSAI1R              (2 << 25)
+#define STM32_PLLSAI1R              (2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
 
 #elif STM32_PLLSAI1R_VALUE == 8
-#define STM32_PLLSAI1R              (3 << 25)
+#define STM32_PLLSAI1R              (3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
 
 #else
 #error "invalid STM32_PLLSAI1R_VALUE value specified"
@@ -295,8 +307,8 @@
 #endif
 
 #else /* !STM32_RCC_PLLSAI1_HAS_R */
-#define STM32_PLLSAI1R              0
-#define STM32_PLLSAI1REN            0
+#define STM32_PLLSAI1R              0U
+#define STM32_PLLSAI1REN            0U
 #endif /* !STM32_RCC_PLLSAI1_HAS_R */
 
 /*===========================================================================*/
@@ -323,15 +335,17 @@ static inline void pllsai1_init(void) {
   RCC->CR |= RCC_CR_PLLSAI1ON;
 
   /* Waiting for PLL lock.*/
-  while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
+  while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0U)
     ;
 #endif
 }
 
 static inline void pllsai1_deinit(void) {
 
+#if STM32_ACTIVATE_PLLSAI1
   /* PLLSAI1 de-activation.*/
   RCC->PLLSAI1CFGR &= ~RCC_CR_PLLSAI1ON;
+#endif
 }
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
index 5cb10bd50..b1e102d1d 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
@@ -26,6 +26,11 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+/* Required for compatibility with those devices with a common M divider.*/
+#if !defined(RCC_PLLSAI1CFGR_PLLSAI2M_Pos)
+#define RCC_PLLSAI1CFGR_PLLSAI2M_Pos    RCC_PLLCFGR_PLLM_Pos
+#endif
+
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
@@ -138,7 +143,7 @@
  */
 #if ((STM32_PLLSAI2M_VALUE >= 1) && (STM32_PLLSAI2M_VALUE <= 16)) ||        \
     defined(__DOXYGEN__)
-#define STM32_PLLSAI2M              ((STM32_PLLSAI2M_VALUE - 1) << 4)
+#define STM32_PLLSAI2M              ((STM32_PLLSAI2M_VALUE - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)
 
 #else
 #error "invalid STM32_PLLSAI2M_VALUE value specified"
@@ -149,7 +154,7 @@
  */
 #if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 127)) ||       \
     defined(__DOXYGEN__)
-#define STM32_PLLSAI2N              (STM32_PLLSAI2N_VALUE << 8)
+#define STM32_PLLSAI2N              (STM32_PLLSAI2N_VALUE << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
 
 #else
 #error "invalid STM32_PLLSAI2N_VALUE value specified"
@@ -176,21 +181,23 @@
  * @brief   STM32_PLLSAI2P field.
  */
 #if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2P              (0 << 17)
+#define STM32_PLLSAI2P              (0U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
 
 #elif STM32_PLLSAI2P_VALUE == 17
-#define STM32_PLLSAI2P              (1 << 17)
+#define STM32_PLLSAI2P              (1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
 
 #else
 #error "invalid STM32_PLLSAI2P_VALUE value specified"
 #endif
 
+/* SAI2PDIV is not present on all devices.*/
+#if defined(RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) || defined(__DOXYGEN__)
 /**
  * @brief   STM32_PLLSAI2PDIV field.
  */
 #if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) ||  \
     defined(__DOXYGEN__)
-#define STM32_PLLSAI2PDIV           (STM32_PLLSAI2PDIV_VALUE << 27)
+#define STM32_PLLSAI2PDIV           (STM32_PLLSAI2PDIV_VALUE << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)
 #else
 #error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
 #endif
@@ -204,6 +211,11 @@
 #define STM32_PLLSAI2_P_CLKOUT      (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
 #endif
 
+#else
+#define STM32_PLLSAI2PDIV           0U
+#define STM32_PLLSAI2_P_CLKOUT      (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
+#endif
+
 /*
  * PLLSAI2-P output frequency range check.
  */
@@ -213,8 +225,8 @@
 #endif
 
 #else /* !STM32_RCC_PLLSAI2_HAS_P */
-#define STM32_PLLSAI2P              0
-#define STM32_PLLSAI2PEN            0
+#define STM32_PLLSAI2P              0U
+#define STM32_PLLSAI2PEN            0U
 #endif /* !STM32_RCC_PLLSAI2_HAS_P */
 
 /*---------------------------------------------------------------------------*/
@@ -225,16 +237,16 @@
  * @brief   STM32_PLLSAI2Q field.
  */
 #if (STM32_PLLSAI2Q_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2Q              (0 << 21)
+#define STM32_PLLSAI2Q              (0U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
 
 #elif STM32_PLLSAI2Q_VALUE == 4
-#define STM32_PLLSAI2Q              (1 << 21)
+#define STM32_PLLSAI2Q              (1U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
 
 #elif STM32_PLLSAI2Q_VALUE == 6
-#define STM32_PLLSAI2Q              (2 << 21)
+#define STM32_PLLSAI2Q              (2U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
 
 #elif STM32_PLLSAI2Q_VALUE == 8
-#define STM32_PLLSAI2Q              (3 << 21)
+#define STM32_PLLSAI2Q              (3U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
 
 #else
 #error "invalid STM32_PLLSAI2Q_VALUE value specified"
@@ -248,14 +260,14 @@
 /*
  * PLLSAI2-Q output frequency range check.
  */
-#if STM32_ACTIVATE_PLLSAI2 &&                                                   \
+#if STM32_ACTIVATE_PLLSAI2 &&                                               \
     ((STM32_PLLSAI2_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI2_Q_CLKOUT > STM32_PLLQ_MAX))
 #error "STM32_PLLSAI2_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
 #endif
 
 #else /* !STM32_RCC_PLLSAI2_HAS_Q */
-#define STM32_PLLSAI2Q              0
-#define STM32_PLLSAI2QEN            0
+#define STM32_PLLSAI2Q              0U
+#define STM32_PLLSAI2QEN            0U
 #endif /* !STM32_RCC_PLLSAI2_HAS_Q */
 
 /*---------------------------------------------------------------------------*/
@@ -266,16 +278,16 @@
  * @brief   STM32_PLLSAI2R field.
  */
 #if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2R              (0 << 25)
+#define STM32_PLLSAI2R              (0U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
 
 #elif STM32_PLLSAI2R_VALUE == 4
-#define STM32_PLLSAI2R              (1 << 25)
+#define STM32_PLLSAI2R              (1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
 
 #elif STM32_PLLSAI2R_VALUE == 6
-#define STM32_PLLSAI2R              (2 << 25)
+#define STM32_PLLSAI2R              (2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
 
 #elif STM32_PLLSAI2R_VALUE == 8
-#define STM32_PLLSAI2R              (3 << 25)
+#define STM32_PLLSAI2R              (3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
 
 #else
 #error "invalid STM32_PLLSAI2R_VALUE value specified"
@@ -295,8 +307,8 @@
 #endif
 
 #else /* !STM32_RCC_PLLSAI2_HAS_R */
-#define STM32_PLLSAI2R              0
-#define STM32_PLLSAI2REN            0
+#define STM32_PLLSAI2R              0U
+#define STM32_PLLSAI2REN            0U
 #endif /* !STM32_RCC_PLLSAI2_HAS_R */
 
 /*===========================================================================*/
@@ -323,15 +335,17 @@ static inline void pllsai2_init(void) {
   RCC->CR |= RCC_CR_PLLSAI2ON;
 
   /* Waiting for PLL lock.*/
-  while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0)
+  while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0U)
     ;
 #endif
 }
 
 static inline void pllsai2_deinit(void) {
 
+#if STM32_ACTIVATE_PLLSAI2
   /* PLLSAI2 de-activation.*/
   RCC->PLLSAI2CFGR &= ~RCC_CR_PLLSAI2ON;
+#endif
 }
 
 /*===========================================================================*/