git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1852 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -43,12 +43,12 @@
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#define IRCOSCCLK 12000000 /**< High speed internal clock. */
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#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */
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#define SYSPLLCLKSEL_IRCOCS 0 /**< Internal RC oscillator
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#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator
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clock source. */
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#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock
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source. */
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#define SYSMAINCLKSEL_IRCOCS 0 /**< Clock source is IRC. */
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#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */
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#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */
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#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */
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#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */
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@ -71,7 +71,7 @@ void hal_lld_init(void) {
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/* SysTick initialization using the system clock.*/
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
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SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1;
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SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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@ -86,30 +86,30 @@ void LPC13xx_clock_init(void) {
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unsigned i;
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/* Flash wait states setting, the code takes care to not touch TBD bits.*/
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FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM;
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FLASHCFG = (FLASHCFG & ~3) | LPC13xx_FLASHCFG_FLASHTIM;
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/* System oscillator initialization if required.*/
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#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
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#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
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LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL;
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#if LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
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#if LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
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LPC_SYSCON->SYSOSCCTRL = LPC13xx_SYSOSCCTRL;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */
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for (i = 0; i < 200; i++)
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__NOP(); /* Stabilization delay. */
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#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
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#endif /* LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
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/* PLL initialization if required.*/
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LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE;
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LPC_SYSCON->SYSPLLCLKSEL = LPC13xx_PLLCLK_SOURCE;
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LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */
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LPC_SYSCON->SYSPLLCLKUEN = 0;
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LPC_SYSCON->SYSPLLCLKUEN = 1;
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LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL;
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LPC_SYSCON->SYSPLLCTRL = LPC13xx_SYSPLLCTRL_MSEL | LPC13xx_SYSPLLCTRL_PSEL;
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LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */
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while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */
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;
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#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
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#endif /* LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
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/* Main clock source selection.*/
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LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE;
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LPC_SYSCON->MAINCLKSEL = LPC13xx_MAINCLK_SOURCE;
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LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */
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LPC_SYSCON->MAINCLKUEN = 0;
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LPC_SYSCON->MAINCLKUEN = 1;
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@ -119,11 +119,11 @@ void LPC13xx_clock_init(void) {
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/* ABH divider initialization, peripheral clocks are initially disabled,
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the various device drivers will handle their own setup except GPIO and
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IOCON that are left enabled.*/
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LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV;
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LPC_SYSCON->SYSAHBCLKDIV = LPC13xx_SYSABHCLK_DIV;
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LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;
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/* Peripheral clock dividers initialization.*/
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LPC_SYSCON->UARTCLKDIV = LPC11xx_UART_PCLK_DIV;
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LPC_SYSCON->UARTCLKDIV = LPC13xx_UART_PCLK_DIV;
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/* Memory remapping, vectors always in ROM.*/
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LPC_SYSCON->SYSMEMREMAP = 2;
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@ -43,12 +43,12 @@
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#define IRCOSCCLK 12000000 /**< High speed internal clock. */
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#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */
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#define SYSPLLCLKSEL_IRCOCS 0 /**< Internal RC oscillator
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#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator
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clock source. */
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#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock
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source. */
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#define SYSMAINCLKSEL_IRCOCS 0 /**< Clock source is IRC. */
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#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */
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#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */
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#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */
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#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */
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@ -60,8 +60,8 @@
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/**
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* @brief System PLL clock source.
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*/
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#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
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#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
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#endif
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/**
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@ -69,39 +69,39 @@
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* @note The value must be in the 1..32 range and the final frequency
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* must not exceed the CCO ratings.
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*/
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#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLL_MUL 4
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#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__)
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#define LPC13xx_SYSPLL_MUL 6
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#endif
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/**
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* @brief System PLL divider.
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* @note The value must be chosen between (2, 4, 8, 16).
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*/
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#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLL_DIV 4
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#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__)
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#define LPC13xx_SYSPLL_DIV 4
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#endif
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/**
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* @brief System main clock source.
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*/
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#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
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#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
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#endif
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/**
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* @brief AHB clock divider.
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* @note The value must be chosen between (1...255).
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*/
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#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__)
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#define LPC11xx_SYSABHCLK_DIV 1
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#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__)
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#define LPC13xx_SYSABHCLK_DIV 1
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#endif
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/**
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* @brief UART clock divider.
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* @note The value must be chosen between (1...255).
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*/
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#if !defined(LPC11xx_UART_PCLK_DIV) || defined(__DOXYGEN__)
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#define LPC11xx_UART_PCLK_DIV 1
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#if !defined(LPC13xx_UART_PCLK_DIV) || defined(__DOXYGEN__)
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#define LPC13xx_UART_PCLK_DIV 1
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#endif
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/*===========================================================================*/
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@ -112,79 +112,79 @@
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* @brief Calculated SYSOSCCTRL setting.
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*/
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#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
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#define LPC11xx_SYSOSCCTRL 0
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#define LPC13xx_SYSOSCCTRL 0
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#else
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#define LPC11xx_SYSOSCCTRL 1
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#define LPC13xx_SYSOSCCTRL 1
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLLCLKIN SYSOSCCLK
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#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS
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#define LPC11xx_SYSPLLCLKIN IRCOSCCLK
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#if (LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
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#define LPC13xx_SYSPLLCLKIN SYSOSCCLK
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#elif LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS
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#define LPC13xx_SYSPLLCLKIN IRCOSCCLK
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#else
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#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified"
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#error "invalid LPC13xx_PLLCLK_SOURCE clock source specified"
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#endif
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/**
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* @brief MSEL mask in SYSPLLCTRL register.
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*/
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#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \
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#if (LPC13xx_SYSPLL_MUL >= 1) && (LPC13xx_SYSPLL_MUL <= 32) || \
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defined(__DOXYGEN__)
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#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1)
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#define LPC13xx_SYSPLLCTRL_MSEL (LPC13xx_SYSPLL_MUL - 1)
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#else
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#error "LPC11xx_SYSPLL_MUL out of range (1...32)"
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#error "LPC13xx_SYSPLL_MUL out of range (1...32)"
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#endif
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/**
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* @brief PSEL mask in SYSPLLCTRL register.
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*/
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#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5)
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#elif LPC11xx_SYSPLL_DIV == 4
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#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5)
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#elif LPC11xx_SYSPLL_DIV == 8
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#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5)
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#elif LPC11xx_SYSPLL_DIV == 16
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#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5)
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#if (LPC13xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
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#define LPC13xx_SYSPLLCTRL_PSEL (0 << 5)
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#elif LPC13xx_SYSPLL_DIV == 4
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#define LPC13xx_SYSPLLCTRL_PSEL (1 << 5)
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#elif LPC13xx_SYSPLL_DIV == 8
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#define LPC13xx_SYSPLLCTRL_PSEL (2 << 5)
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#elif LPC13xx_SYSPLL_DIV == 16
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#define LPC13xx_SYSPLLCTRL_PSEL (3 << 5)
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#else
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#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)"
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#error "invalid LPC13xx_SYSPLL_DIV value (2,4,8,16)"
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#endif
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/**
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* @brief CCP frequency.
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*/
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#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL * \
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LPC11xx_SYSPLL_DIV)
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#define LPC13xx_SYSPLLCCO (LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL * \
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LPC13xx_SYSPLL_DIV)
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#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000)
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#if (LPC13xx_SYSPLLCCO < 156000000) || (LPC13xx_SYSPLLCCO > 320000000)
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#error "CCO frequency out of the acceptable range (156...320)"
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#endif
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/**
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* @brief PLL output clock frequency.
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*/
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#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
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#define LPC13xx_SYSPLLCLKOUT (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV)
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#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)
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#define LPC11xx_MAINCLK IRCOSCCLK
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#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
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#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN
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#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
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#define LPC11xx_MAINCLK WDGOSCCLK
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#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
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#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT
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#if (LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)
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#define LPC13xx_MAINCLK IRCOSCCLK
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#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
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#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKIN
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#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
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#define LPC13xx_MAINCLK WDGOSCCLK
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#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
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#define LPC13xx_MAINCLK LPC13xx_SYSPLLCLKOUT
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#else
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#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified"
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#error "invalid LPC13xx_MAINCLK_SOURCE clock source specified"
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#endif
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/**
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* @brief AHB clock.
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*/
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#if (LPC11xx_SYSCLK <= 50000000) || defined(__DOXYGEN__)
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#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
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#if (LPC13xx_SYSCLK <= 50000000) || defined(__DOXYGEN__)
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#define LPC13xx_SYSCLK (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV)
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#else
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#error "AHB clock frequency out of the acceptable range (50MHz max)"
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#endif
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/**
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* @brief Flash wait states.
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*/
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#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
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#define LPC11xx_FLASHCFG_FLASHTIM 0
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#elif LPC11xx_SYSCLK <= 40000000
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#define LPC11xx_FLASHCFG_FLASHTIM 1
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#if (LPC13xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
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#define LPC13xx_FLASHCFG_FLASHTIM 0
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#elif LPC13xx_SYSCLK <= 40000000
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#define LPC13xx_FLASHCFG_FLASHTIM 1
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#else
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#define LPC11xx_FLASHCFG_FLASHTIM 2
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#define LPC13xx_FLASHCFG_FLASHTIM 2
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#endif
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/**
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* @brief UART clock.
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*/
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#define LPC11xx_UART_PCLK (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)
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#define LPC13xx_UART_PCLK (LPC13xx_MAINCLK / LPC13xx_UART_PCLK_DIV)
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/*===========================================================================*/
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/* Driver data structures and types. */
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@ -62,7 +62,7 @@ static const SerialConfig default_config = {
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static void uart_init(SerialDriver *sdp) {
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LPC_UART_TypeDef *u = sdp->uart;
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uint32_t div = LPC11xx_UART_PCLK / (sdp->config->sc_speed << 4);
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uint32_t div = LPC13xx_UART_PCLK / (sdp->config->sc_speed << 4);
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u->LCR = sdp->config->sc_lcr | LCR_DLAB;
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u->DLL = div;
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u->DLM = div >> 8;
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