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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1827 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-04-02 08:59:10 +00:00
parent ee8e0c61f9
commit 876463f721
19 changed files with 53 additions and 4454 deletions
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4
demos/ARMCM3-STM32F103-FATFS-GCC/Makefile
View File

@ -60,7 +60,7 @@ CHIBIOS = ../..
include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
include $(CHIBIOS)/ext/fatfs/fatfs.mk
@ -104,7 +104,7 @@ TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM) \
$(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \

2
demos/ARMCM3-STM32F103-GCC/Makefile
View File

@ -102,7 +102,7 @@ TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM) \
$(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \

2
os/hal/platforms/STM32/pwm_lld.c
View File

@ -274,7 +274,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
NVICEnableVector(TIM1_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY));
NVICEnableVector(TIM1_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY);
CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY));
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
}
#endif

56
os/ports/GCC/ARMCM3/STM32F103/cmparams.h
View File

@ -1,56 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/STM32F103/cmparams.h
* @brief ARM Cortex-M3 STM32F10x specific parameters.
*
* @defgroup ARMCM3_STM32F10x STM32F10x specific parameters
* @ingroup ARMCM3
* @details This file contains the Cortex-M3 specific parameters for the
* STM32F10x platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU FALSE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 4
#endif /* _CMPARAMS_H_ */
/** @} */

10
os/ports/GCC/ARMCM3/STM32F103/port.mk
View File

@ -1,10 +0,0 @@
# List of the ChibiOS/RT Cortex-M3 port files.
PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCM3/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCM3/nvic.c \
${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis/core_cm3.c
PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCM3/crt0.s
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCM3 \
${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103 \
${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis

363
os/ports/GCC/ARMCM3/STM32F103/vectors.s
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@ -1,363 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
.syntax unified
.thumb
.section vectors
_vectors:
.word __ram_end__
.word ResetHandler
.word NMIVector
.word HardFaultVector
.word MemManageVector
.word BusFaultVector
.word UsageFaultVector
.word Vector1C
.word Vector20
.word Vector24
.word Vector28
.word SVCallVector
.word DebugMonitorVector
.word Vector34
.word PendSVVector
.word SysTickVector
.word Vector40
.word Vector44
.word Vector48
.word Vector4C
.word Vector50
.word Vector54
.word Vector58
.word Vector5C
.word Vector60
.word Vector64
.word Vector68
.word Vector6C
.word Vector70
.word Vector74
.word Vector78
.word Vector7C
.word Vector80
.word Vector84
.word Vector88
.word Vector8C
.word Vector90
.word Vector94
.word Vector98
.word Vector9C
.word VectorA0
.word VectorA4
.word VectorA8
.word VectorAC
.word VectorB0
.word VectorB4
.word VectorB8
.word VectorBC
.word VectorC0
.word VectorC4
.word VectorC8
.word VectorCC
.word VectorD0
.word VectorD4
.word VectorD8
.word VectorDC
.word VectorE0
.word VectorE4
.word VectorE8
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
.word VectorEC
.word VectorF0
.word VectorF4
.word VectorF8
.word VectorFC
.word Vector100
.word Vector104
.word Vector108
.word Vector10C
.word Vector110
.word Vector114
.word Vector118
.word Vector11C
.word Vector120
.word Vector124
.word Vector128
.word Vector12C
#endif
#if defined(STM32F10X_CL)
.word Vector130
.word Vector134
.word Vector138
.word Vector13C
.word Vector140
.word Vector144
.word Vector148
.word Vector14C
#endif
.weak NMIVector
NMIVector:
.weak HardFaultVector
HardFaultVector:
.weak MemManageVector
MemManageVector:
.weak BusFaultVector
BusFaultVector:
.weak UsageFaultVector
UsageFaultVector:
.weak Vector1C
Vector1C:
.weak Vector20
Vector20:
.weak Vector24
Vector24:
.weak Vector28
Vector28:
.weak SVCallVector
SVCallVector:
.weak DebugMonitorVector
DebugMonitorVector:
.weak Vector34
Vector34:
.weak PendSVVector
PendSVVector:
.weak SysTickVector
SysTickVector:
.weak Vector40
Vector40:
.weak Vector44
Vector44:
.weak Vector48
Vector48:
.weak Vector4C
Vector4C:
.weak Vector50
Vector50:
.weak Vector54
Vector54:
.weak Vector58
Vector58:
.weak Vector5C
Vector5C:
.weak Vector60
Vector60:
.weak Vector64
Vector64:
.weak Vector68
Vector68:
.weak Vector6C
Vector6C:
.weak Vector70
Vector70:
.weak Vector74
Vector74:
.weak Vector78
Vector78:
.weak Vector7C
Vector7C:
.weak Vector80
Vector80:
.weak Vector84
Vector84:
.weak Vector88
Vector88:
.weak Vector8C
Vector8C:
.weak Vector90
Vector90:
.weak Vector94
Vector94:
.weak Vector98
Vector98:
.weak Vector9C
Vector9C:
.weak VectorA0
VectorA0:
.weak VectorA4
VectorA4:
.weak VectorA8
VectorA8:
.weak VectorAC
VectorAC:
.weak VectorB0
VectorB0:
.weak VectorB4
VectorB4:
.weak VectorB8
VectorB8:
.weak VectorBC
VectorBC:
.weak VectorC0
VectorC0:
.weak VectorC4
VectorC4:
.weak VectorC8
VectorC8:
.weak VectorCC
VectorCC:
.weak VectorD0
VectorD0:
.weak VectorD4
VectorD4:
.weak VectorD8
VectorD8:
.weak VectorDC
VectorDC:
.weak VectorE0
VectorE0:
.weak VectorE4
VectorE4:
.weak VectorE8
VectorE8:
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
.weak VectorEC
VectorEC:
.weak VectorF0
VectorF0:
.weak VectorF4
VectorF4:
.weak VectorF8
VectorF8:
.weak VectorFC
VectorFC:
.weak Vector100
Vector100:
.weak Vector104
Vector104:
.weak Vector108
Vector108:
.weak Vector10C
Vector10C:
.weak Vector110
Vector110:
.weak Vector114
Vector114:
.weak Vector118
Vector118:
.weak Vector11C
Vector11C:
.weak Vector120
Vector120:
.weak Vector124
Vector124:
.weak Vector128
Vector128:
.weak Vector12C
Vector12C:
#endif
#if defined(STM32F10X_CL)
.weak Vector130
Vector130:
.weak Vector134
Vector134:
.weak Vector138
Vector138:
.weak Vector13C
Vector13C:
.weak Vector140
Vector140:
.weak Vector144
Vector144:
.weak Vector148
Vector148:
.weak Vector14C
Vector14C:
#endif
here: b here

194
os/ports/GCC/ARMCM3/chcore.c
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@ -1,194 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/chcore.c
* @brief ARM Cortex-M3 architecture port code.
*
* @addtogroup ARMCM3_CORE
* @{
*/
#include "ch.h"
#include "nvic.h"
/**
* @brief Halts the system.
* @note The function is declared as a weak symbol, it is possible
* to redefine it in your application code.
*/
#if !defined(__DOXYGEN__)
__attribute__((weak))
#endif
void port_halt(void) {
port_disable();
while (TRUE) {
}
}
#if !CH_OPTIMIZE_SPEED
void _port_lock(void) {
register uint32_t tmp asm ("r3") = BASEPRI_KERNEL;
asm volatile ("msr BASEPRI, %0" : : "r" (tmp));
}
void _port_unlock(void) {
register uint32_t tmp asm ("r3") = BASEPRI_USER;
asm volatile ("msr BASEPRI, %0" : : "r" (tmp));
}
#endif
/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.
* @note The timer must be initialized in the startup code.
*/
void SysTickVector(void) {
chSysLockFromIsr();
chSysTimerHandlerI();
if (chSchIsRescRequiredExI())
SCB_ICSR = ICSR_PENDSVSET;
chSysUnlockFromIsr();
}
#if CORTEX_MODEL == CORTEX_M0
#define PUSH_CONTEXT(sp, prio) { \
asm volatile ("mrs %0, PSP \n\t" \
"sub %0, %0, #40 \n\t" \
"stmia %0!, {r3-r7} \n\t" \
"sub %0, %0, #20 \n\t" \
"mov r3, r8 \n\t" \
"str r3, [%0, #20] \n\t" \
"mov r3, r9 \n\t" \
"str r3, [%0, #24] \n\t" \
"mov r3, r10 \n\t" \
"str r3, [%0, #28] \n\t" \
"mov r3, r11 \n\t" \
"str r3, [%0, #32] \n\t" \
"mov r3, lr \n\t" \
"str r3, [%0, #36] \n\t" \
: "=r" (sp) : "r" (sp), "r" (prio)); \
}
#define POP_CONTEXT(sp) { \
asm volatile ("ldr r3, [%0, #20] \n\t" \
"mov r8, r3 \n\t" \
"ldr r3, [%0, #24] \n\t" \
"mov r9, r3 \n\t" \
"ldr r3, [%0, #28] \n\t" \
"mov r10, r3 \n\t" \
"ldr r3, [%0, #32] \n\t" \
"mov r11, r3 \n\t" \
"ldr r3, [%0, #36] \n\t" \
"mov lr, r3 \n\t" \
"ldmia %0!, {r3-r7} \n\t" \
"add %0, %0, #20 \n\t" \
"msr PSP, %0 \n\t" \
"msr BASEPRI, r3 \n\t" \
"bx lr" : "=r" (sp) : "r" (sp)); \
}
#else /* CORTEX_MODEL != CORTEX_M0 */
#if !defined(CH_CURRP_REGISTER_CACHE)
#define PUSH_CONTEXT(sp, prio) { \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r11,lr}" : \
"=r" (sp) : "r" (sp), "r" (prio)); \
}
#define POP_CONTEXT(sp) { \
asm volatile ("ldmia %0!, {r3-r11, lr} \n\t" \
"msr PSP, %0 \n\t" \
"msr BASEPRI, r3 \n\t" \
"bx lr" : "=r" (sp) : "r" (sp)); \
}
#else /* defined(CH_CURRP_REGISTER_CACHE) */
#define PUSH_CONTEXT(sp, prio) { \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r6,r8-r11, lr}" : \
"=r" (sp) : "r" (sp), "r" (prio)); \
}
#define POP_CONTEXT(sp) { \
asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr} \n\t" \
"msr PSP, %0 \n\t" \
"msr BASEPRI, r3 \n\t" \
"bx lr" : "=r" (sp) : "r" (sp)); \
}
#endif /* defined(CH_CURRP_REGISTER_CACHE) */
#endif /* CORTEX_MODEL != CORTEX_M0 */
/**
* @brief SVC vector.
* @details The SVC vector is used for commanded context switch. Structures
* @p intctx are saved and restored from the process stacks of the
* switched threads.
*
* @param[in] ntp the thread to be switched it
* @param[in] otp the thread to be switched out
*/
#if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
void SVCallVector(Thread *ntp, Thread *otp) {
register struct intctx *sp_thd asm("r2");
register uint32_t prio asm ("r3");
asm volatile ("mrs r3, BASEPRI" : "=r" (prio) : );
PUSH_CONTEXT(sp_thd, prio)
otp->p_ctx.r13 = sp_thd;
sp_thd = ntp->p_ctx.r13;
POP_CONTEXT(sp_thd)
}
/**
* @brief Preemption code.
*/
#if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
void PendSVVector(void) {
register struct intctx *sp_thd asm("r2");
register uint32_t prio asm ("r3");
Thread *otp, *ntp;
chSysLockFromIsr();
prio = CORTEX_BASEPRI_USER;
PUSH_CONTEXT(sp_thd, prio)
(otp = currp)->p_ctx.r13 = sp_thd;
ntp = fifo_remove(&rlist.r_queue);
setcurrp(ntp);
ntp->p_state = THD_STATE_CURRENT;
chSchReadyI(otp);
#if CH_TIME_QUANTUM > 0
/* Set the round-robin time quantum.*/
rlist.r_preempt = CH_TIME_QUANTUM;
#endif
chDbgTrace(otp);
sp_thd = ntp->p_ctx.r13;
POP_CONTEXT(sp_thd)
}
/** @} */

501
os/ports/GCC/ARMCM3/chcore.h
View File

@ -1,501 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/chcore.h
* @brief ARM Cortex-M3 architecture port macros and structures.
*
* @addtogroup ARMCM3_CORE
* @{
*/
#ifndef _CHCORE_H_
#define _CHCORE_H_
#include "nvic.h"
/*===========================================================================*/
/* Port constants. */
/*===========================================================================*/
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
/* Cortex model check, only M3 right now.*/
#if (CORTEX_MODEL == CORTEX_M3)
#else
#error "unknown or unsupported Cortex-M model"
#endif
/*===========================================================================*/
/* Port derived parameters. */
/*===========================================================================*/
/**
* @brief Priority masking support.
*/
#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__)
#define CORTEX_SUPPORTS_BASEPRI TRUE
#else
#define CORTEX_SUPPORTS_BASEPRI FALSE
#endif
/**
* @brief Total priority levels.
*/
#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
#define CORTEX_MAXIMUM_PRIORITY 0
/*===========================================================================*/
/* Port macros. */
/*===========================================================================*/
/**
* @brief Priority level verification macro.
*/
#define CORTEX_IS_VALID_PRIORITY(n) \
(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
/**
* @brief Priority level to priority mask conversion macro.
*/
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
/* Port configurable parameters. */
/*===========================================================================*/
/**
* @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#ifndef CORTEX_ENABLE_WFI_IDLE
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
* @brief SYSTICK handler priority.
* @note The default is calculated as the priority level in the middle
* of the priority range.
*/
#ifndef CORTEX_PRIORITY_SYSTICK
#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#else
/* If it is externally redefined then better perform a validity check on it.*/
#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif
#endif
/**
* @brief BASEPRI user level.
*/
#ifndef CORTEX_BASEPRI_USER
#define CORTEX_BASEPRI_USER 0
#endif
/**
* @brief BASEPRI level within kernel lock.
* @details Priority levels higher than this one (lower values) are unaffected
* by the OS activity and can be classified as fast interrupt sources,
* see @ref interrupt_classes.
*/
#ifndef CORTEX_BASEPRI_KERNEL
#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAXIMUM_PRIORITY+4)
#endif
/**
* @brief PENDSV handler priority.
* @note This priority must always be the lowest one.
* @note It is recommended, but not mandatory, to leave this priority level
* for this handler alone.
*/
#ifndef CORTEX_PRIORITY_PENDSV
#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
#endif
/**
* @brief SVCALL handler priority.
* @note This priority must always be one level above the
* @p CORTEX_MAXIMUM_PRIORITY value.
* @note It is recommended, but not mandatory, to leave this priority level
* for this handler alone.
*/
#ifndef CORTEX_PRIORITY_SVCALL
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 3)
#endif
/*===========================================================================*/
/* Port exported info. */
/*===========================================================================*/
#if defined(__DOXYGEN__)
/**
* @brief Macro defining the ARM architecture.
*/
#define CH_ARCHITECTURE_ARM_vxm
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "ARMvx-M"
/**
* @brief Name of the architecture variant (optional).
*/
#define CH_CORE_VARIANT_NAME "Cortex-Mx"
#elif CORTEX_MODEL == CORTEX_M4
#define CH_ARCHITECTURE_ARM_v7M
#define CH_ARCHITECTURE_NAME "ARMv7-M"
#define CH_CORE_VARIANT_NAME "Cortex-M4"
#elif CORTEX_MODEL == CORTEX_M3
#define CH_ARCHITECTURE_ARM_v7M
#define CH_ARCHITECTURE_NAME "ARMv7-M"
#define CH_CORE_VARIANT_NAME "Cortex-M3"
#elif CORTEX_MODEL == CORTEX_M1
#define CH_ARCHITECTURE_ARM_v6M
#define CH_ARCHITECTURE_NAME "ARMv6-M"
#define CH_CORE_VARIANT_NAME "Cortex-M1"
#elif CORTEX_MODEL == CORTEX_M0
#define CH_ARCHITECTURE_ARM_v6M
#define CH_ARCHITECTURE_NAME "ARMv6-M"
#define CH_CORE_VARIANT_NAME "Cortex-M0"
#endif
/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
/**
* @brief 32 bits stack and memory alignment enforcement.
*/
typedef uint32_t stkalign_t;
/**
* @brief Generic ARM register.
*/
typedef void *regarm_t;
#if !defined(__DOXYGEN__)
/**
* @brief Interrupt saved context.
* @details This structure represents the stack frame saved during a
* preemption-capable interrupt handler.
* @note This structure is empty in this port.
*/
struct extctx {
};
#endif
#if !defined(__DOXYGEN__)
/**
* @brief System saved context.
* @details This structure represents the inner stack frame during a context
* switching.
*/
struct intctx {
regarm_t basepri;
regarm_t r4;
regarm_t r5;
regarm_t r6;
#ifndef CH_CURRP_REGISTER_CACHE
regarm_t r7;
#endif
regarm_t r8;
regarm_t r9;
regarm_t r10;
regarm_t r11;
regarm_t lr_exc;
/* Start of the hardware saved frame.*/
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t r12;
regarm_t lr_thd;
regarm_t pc;
regarm_t xpsr;
};
#endif
#if !defined(__DOXYGEN__)
/**
* @brief Platform dependent part of the @p Thread structure.
* @details In the Cortex-M3 port this structure just holds a pointer to the
* @p intctx structure representing the stack pointer at the time
* of the context switch.
*/
struct context {
struct intctx *r13;
};
#endif
/**
* @brief Platform dependent part of the @p chThdInit() API.
* @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
wsize - \
sizeof(struct intctx)); \
tp->p_ctx.r13->basepri = CORTEX_BASEPRI_USER; \
tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \
tp->p_ctx.r13->r0 = arg; \
tp->p_ctx.r13->lr_thd = chThdExit; \
tp->p_ctx.r13->pc = pf; \
tp->p_ctx.r13->xpsr = (regarm_t)0x01000000; \
}
/**
* @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
* by @p INT_REQUIRED_STACK.
* @note In this port it is set to 4 because the idle thread does have
* a stack frame when compiling without optimizations.
*/
#ifndef IDLE_THREAD_STACK_SIZE
#define IDLE_THREAD_STACK_SIZE 4
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* This value can be zero on those architecture where there is a
* separate interrupt stack and the stack space between @p intctx and
* @p extctx is known to be zero.
* @note This port requires no extra stack space for interrupt handling.
*/
#ifndef INT_REQUIRED_STACK
#define INT_REQUIRED_STACK 0
#endif
/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
/**
* @brief Computes the thread working area global size.
*/
#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
sizeof(struct intctx) + \
sizeof(struct extctx) + \
(n) + (INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
* @details This macro is used to allocate a static thread working area
* aligned as both position and size.
*/
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_PROLOGUE()
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() { \
chSysLockFromIsr(); \
if (chSchIsRescRequiredI()) \
SCB_ICSR = ICSR_PENDSVSET; \
chSysUnlockFromIsr(); \
}
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_IRQ_HANDLER(id) void id(void)
/**
* @brief Port-related initialization code.
*/
#define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
/**
* @brief Kernel-lock action.
* @details Usually this function just disables interrupts but may perform
* more actions.
* @note In this port this it raises the base priority to kernel level.
*/
#if CH_OPTIMIZE_SPEED
#define port_lock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
#else
#define port_lock() { \
asm volatile ("bl _port_lock" : : : "r3", "lr"); \
}
#endif
/**
* @brief Kernel-unlock action.
* @details Usually this function just disables interrupts but may perform
* more actions.
* @note In this port this it lowers the base priority to kernel level.
*/
#if CH_OPTIMIZE_SPEED
#define port_unlock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
#else
#define port_unlock() { \
asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
}
#endif
/**
* @brief Kernel-lock action from an interrupt handler.
* @details This function is invoked before invoking I-class APIs from
* interrupt handlers. The implementation is architecture dependent,
* in its simplest form it is void.
* @note Same as @p port_lock() in this port.
*/
#define port_lock_from_isr() port_lock()
/**
* @brief Kernel-unlock action from an interrupt handler.
* @details This function is invoked after invoking I-class APIs from interrupt
* handlers. The implementation is architecture dependent, in its
* simplest form it is void.
* @note Same as @p port_unlock() in this port.
*/
#define port_unlock_from_isr() port_unlock()
/**
* @brief Disables all the interrupt sources.
* @note Of course non maskable interrupt sources are not included.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
#define port_disable() asm volatile ("cpsid i")
/**
* @brief Disables the interrupt sources below kernel-level priority.
* @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
#define port_suspend() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \
}
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
#define port_enable() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \
}
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
* @details The function is meant to return when an interrupt becomes pending.
* The simplest implementation is an empty function or macro but this
* would not take advantage of architecture-specific power saving
* modes.
* @note Implemented as an inlined @p WFI instruction.
*/
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() { \
asm volatile ("wfi"); \
}
#else
#define port_wait_for_interrupt()
#endif
/**
* @brief Performs a context switch between two threads.
* @details This is the most critical code in any port, this function
* is responsible for the context switch between 2 threads.
* @note The implementation of this code affects <b>directly</b> the context
* switch performance so optimize here as much as you can.
* @note Implemented as inlined code for performance reasons.
*
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
static INLINE Thread *port_switch(Thread *ntp, Thread *otp) {
register Thread *_ntp asm ("r0") = (ntp);
register Thread *_otp asm ("r1") = (otp);
#if CH_DBG_ENABLE_STACK_CHECK
register char *sp asm ("sp");
if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp)
asm volatile ("movs r0, #0 \n\t"
"b chDbgPanic");
#endif /* CH_DBG_ENABLE_STACK_CHECK */
asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp) : "memory");
return _otp;
}
#ifdef __cplusplus
extern "C" {
#endif
void port_halt(void);
#if !CH_OPTIMIZE_SPEED
void _port_lock(void);
void _port_unlock(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CHCORE_H_ */
/** @} */

57
os/ports/GCC/ARMCM3/chtypes.h
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@ -1,57 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/chtypes.h
* @brief ARM Cortex-M3 architecture port system types.
* @addtogroup ARMCM3_CORE
* @{
*/
#ifndef _CHTYPES_H_
#define _CHTYPES_H_
#define __need_NULL
#define __need_size_t
#define __need_ptrdiff_t
#include <stddef.h>
#if !defined(_STDINT_H) && !defined(__STDINT_H_)
#include <stdint.h>
#endif
typedef int32_t bool_t; /**< Fast boolean type. */
typedef uint8_t tmode_t; /**< Thread flags. */
typedef uint8_t tstate_t; /**< Thread state. */
typedef uint8_t trefs_t; /**< Thread references counter. */
typedef uint32_t tprio_t; /**< Thread priority. */
typedef int32_t msg_t; /**< Inter-thread message. */
typedef int32_t eventid_t; /**< Event Id. */
typedef uint32_t eventmask_t; /**< Events mask. */
typedef uint32_t systime_t; /**< System time. */
typedef int32_t cnt_t; /**< Resources counter. */
#define INLINE inline
#define PACK_STRUCT_STRUCT __attribute__((packed))
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_END
#endif /* _CHTYPES_H_ */
/** @} */

784
os/ports/GCC/ARMCM3/cmsis/core_cm3.c
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@ -1,784 +0,0 @@
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

1842
os/ports/GCC/ARMCM3/cmsis/core_cm3.h
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161
os/ports/GCC/ARMCM3/crt0.s
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/crt0.s
* @brief Generic ARM Cortex-M3 startup file for ChibiOS/RT.
* @addtogroup ARMCM3_CORE
* @{
*/
#include "cmparams.h"
#if !defined(__DOXYGEN__)
.set CONTROL_MODE_PRIVILEGED, 0
.set CONTROL_MODE_UNPRIVILEGED, 1
.set CONTROL_USE_MSP, 0
.set CONTROL_USE_PSP, 2
.text
.balign 2
.syntax unified
.thumb
/*
* Reset handler.
*/
.thumb_func
.global ResetHandler
.weak ResetHandler
ResetHandler:
/*
* Interrupts are globally masked initially.
*/
cpsid i
/*
* Stack pointers initialization.
*/
ldr r0, =__ram_end__
ldr r1, =__main_stack_size__
subs r0, r0, r1
/*
* Note that r0 is the main stack low boundary address and process
* stack initial top address.
*/
msr PSP, r0
/*
* Early initialization phase, it is empty by default.
*/
bl hwinit0
/*
* Data initialization.
* NOTE: It assumes that the DATA size is a multiple of 4.
*/
ldr r1, =_textdata
ldr r2, =_data
ldr r3, =_edata
dloop:
cmp r2, r3
#if CORTEX_MODEL == CORTEX_M0
bge enddloop
ldr r0, [r1]
str r0, [r2]
adds r1, r1, #4
adds r2, r2, #4
b dloop
enddloop:
#else
ittt lo
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo dloop
#endif
/*
* BSS initialization.
* NOTE: It assumes that the BSS size is a multiple of 4.
*/
movs r0, #0
ldr r1, =_bss_start
ldr r2, =_bss_end
bloop:
cmp r1, r2
#if CORTEX_MODEL == CORTEX_M0
bge endbloop
str r0, [r1]
adds r1, r1, #4
b bloop
endbloop:
#else
itt lo
strlo r0, [r1], #4
blo bloop
#endif
/*
* Switches to the Process Stack and uses a barrier just to be safe.
*/
movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
msr CONTROL, r0
isb
/*
* Late initialization phase, it is empty by default.
*/
bl hwinit1
movs r0, #0
mov r1, r0
bl main
b MainExitHandler
/*
* Default main exit code, just a loop.
* It is a weak symbol, the application code can redefine the behavior.
*/
.thumb_func
.global MainExitHandler
.weak MainExitHandler
MainExitHandler:
.loop: b .loop
/*
* Default early initialization code. It is declared weak in order to be
* replaced by the real initialization code.
* Early initialization is performed just after reset before BSS and DATA
* segments initialization.
*/
.thumb_func
.global hwinit0
.weak hwinit0
hwinit0:
bx lr
/*
* Default late initialization code. It is declared weak in order to be
* replaced by the real initialization code.
* Late initialization is performed after BSS and DATA segments initialization
* and before invoking the main() function.
*/
.thumb_func
.global hwinit1
.weak hwinit1
hwinit1:
bx lr
#endif
/** @} */

73
os/ports/GCC/ARMCM3/nvic.c
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@ -1,73 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/nvic.c
* @brief Cortex-M3 NVIC support code.
* @addtogroup ARMCM3_NVIC
* @{
*/
#include "ch.h"
#include "nvic.h"
/**
* @brief Sets the priority of an interrupt handler and enables it.
*
* @param n the interrupt number
* @param prio the interrupt priority
*
* @note The parameters are not tested for correctness.
*/
void NVICEnableVector(uint32_t n, uint32_t prio) {
unsigned sh = (n & 3) << 3;
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
}
/**
* @brief Disables an interrupt handler.
*
* @param n the interrupt number
*
* @note The parameters are not tested for correctness.
*/
void NVICDisableVector(uint32_t n) {
unsigned sh = (n & 3) << 3;
NVIC_ICER(n >> 5) = 1 << (n & 0x1F);
NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh);
}
/**
* @brief Changes the priority of a system handler.
*
* @param handler the system handler number
* @param prio the system handler priority
* @note The parameters are not tested for correctness.
*/
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
unsigned sh = (handler & 3) * 8;
SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & ~(0xFF << sh)) | (prio << sh);
}
/** @} */

191
os/ports/GCC/ARMCM3/nvic.h
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@ -1,191 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/nvic.h
* @brief Cortex-M3 NVIC support macros and structures.
* @addtogroup ARMCM3_NVIC
* @{
*/
#ifndef _NVIC_H_
#define _NVIC_H_
/*
* System vector constants for @p NVICSetSystemHandlerPriority().
*/
#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id.*/
#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id.*/
#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id.*/
#define HANDLER_RESERVED_3 3
#define HANDLER_RESERVED_4 4
#define HANDLER_RESERVED_5 5
#define HANDLER_RESERVED_6 6
#define HANDLER_SVCALL 7 /**< SVCALL vector id.*/
#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id.*/
#define HANDLER_RESERVED_9 9
#define HANDLER_PENDSV 10 /**< PENDSV vector id.*/
#define HANDLER_SYSTICK 11 /**< SYS TCK vector id.*/
typedef volatile unsigned char IOREG8; /**< 8 bits I/O register type.*/
typedef volatile unsigned int IOREG32; /**< 32 bits I/O register type.*/
/**
* @brief NVIC ITCR register.
*/
#define NVIC_ITCR (*((IOREG32 *)0xE000E004))
/**
* @brief NVIC STIR register.
*/
#define NVIC_STIR (*((IOREG32 *)0xE000EF00))
/**
* @brief Structure representing the SYSTICK I/O space.
*/
typedef struct {
IOREG32 CSR;
IOREG32 RVR;
IOREG32 CVR;
IOREG32 CBVR;
} CM3_ST;
/**
* @brief SYSTICK peripheral base address.
*/
#define STBase ((CM3_ST *)0xE000E010)
#define ST_CSR (STBase->CSR)
#define ST_RVR (STBase->RVR)
#define ST_CVR (STBase->CVR)
#define ST_CBVR (STBase->CBVR)
#define CSR_ENABLE_MASK (0x1 << 0)
#define ENABLE_OFF_BITS (0 << 0)
#define ENABLE_ON_BITS (1 << 0)
#define CSR_TICKINT_MASK (0x1 << 1)
#define TICKINT_DISABLED_BITS (0 << 1)
#define TICKINT_ENABLED_BITS (1 << 1)
#define CSR_CLKSOURCE_MASK (0x1 << 2)
#define CLKSOURCE_EXT_BITS (0 << 2)
#define CLKSOURCE_CORE_BITS (1 << 2)
#define CSR_COUNTFLAG_MASK (0x1 << 16)
#define RVR_RELOAD_MASK (0xFFFFFF << 0)
#define CVR_CURRENT_MASK (0xFFFFFF << 0)
#define CBVR_TENMS_MASK (0xFFFFFF << 0)
#define CBVR_SKEW_MASK (0x1 << 30)
#define CBVR_NOREF_MASK (0x1 << 31)
/**
* @brief Structure representing the NVIC I/O space.
*/
typedef struct {
IOREG32 ISER[8];
IOREG32 unused1[24];
IOREG32 ICER[8];
IOREG32 unused2[24];
IOREG32 ISPR[8];
IOREG32 unused3[24];
IOREG32 ICPR[8];
IOREG32 unused4[24];
IOREG32 IABR[8];
IOREG32 unused5[56];
IOREG32 IPR[60];
} CM3_NVIC;
/**
* @brief NVIC peripheral base address.
*/
#define NVICBase ((CM3_NVIC *)0xE000E100)
#define NVIC_ISER(n) (NVICBase->ISER[n])
#define NVIC_ICER(n) (NVICBase->ICER[n])
#define NVIC_ISPR(n) (NVICBase->ISPR[n])
#define NVIC_ICPR(n) (NVICBase->ICPR[n])
#define NVIC_IABR(n) (NVICBase->IABR[n])
#define NVIC_IPR(n) (NVICBase->IPR[n])
/**
* @brief Structure representing the System Control Block I/O space.
*/
typedef struct {
IOREG32 CPUID;
IOREG32 ICSR;
IOREG32 VTOR;
IOREG32 AIRCR;
IOREG32 SCR;
IOREG32 CCR;
IOREG32 SHPR[3];
IOREG32 SHCSR;
IOREG32 CFSR;
IOREG32 HFSR;
IOREG32 DFSR;
IOREG32 MMFAR;
IOREG32 BFAR;
IOREG32 AFSR;
} CM3_SCB;
/**
* @brief SCB peripheral base address.
*/
#define SCBBase ((CM3_SCB *)0xE000ED00)
#define SCB_CPUID (SCBBase->CPUID)
#define SCB_ICSR (SCBBase->ICSR)
#define SCB_VTOR (SCBBase->VTOR)
#define SCB_AIRCR (SCBBase->AIRCR)
#define SCB_SCR (SCBBase->SCR)
#define SCB_CCR (SCBBase->CCR)
#define SCB_SHPR(n) (SCBBase->SHPR[n])
#define SCB_SHCSR (SCBBase->SHCSR)
#define SCB_CFSR (SCBBase->CFSR)
#define SCB_HFSR (SCBBase->HFSR)
#define SCB_DFSR (SCBBase->DFSR)
#define SCB_MMFAR (SCBBase->MMFAR)
#define SCB_BFAR (SCBBase->BFAR)
#define SCB_AFSR (SCBBase->AFSR)
#define ICSR_VECTACTIVE_MASK (0x1FF << 0)
#define ICSR_RETTOBASE (0x1 << 11)
#define ICSR_VECTPENDING_MASK (0x1FF << 12)
#define ICSR_ISRPENDING (0x1 << 22)
#define ICSR_ISRPREEMPT (0x1 << 23)
#define ICSR_PENDSTCLR (0x1 << 25)
#define ICSR_PENDSTSET (0x1 << 26)
#define ICSR_PENDSVCLR (0x1 << 27)
#define ICSR_PENDSVSET (0x1 << 28)
#define ICSR_NMIPENDSET (0x1 << 31)
#define AIRCR_VECTKEY 0x05FA0000
#define AIRCR_PRIGROUP_MASK (0x7 << 8)
#define AIRCR_PRIGROUP(n) ((n) << 8)
#ifdef __cplusplus
extern "C" {
#endif
void NVICEnableVector(uint32_t n, uint32_t prio);
void NVICDisableVector(uint32_t n);
void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
#ifdef __cplusplus
}
#endif
#endif /* _NVIC_H_ */
/** @} */

168
os/ports/GCC/ARMCM3/port.dox
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@ -1,168 +0,0 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @defgroup ARMCM3 ARM Cortex-M3
* @details This port supports the ARM Cortex-M3 architecture.
*
* @section ARMCM3_STATES Mapping of the System States in the ARM Cortex-M3 port
* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
* Cortex-M3 port:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
* - <b>Normal</b>. This is the state the system has after executing
* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
* processor is running in thread-privileged mode.
* - <b>Suspended</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in thread-privileged mode.
* - <b>Disabled</b>. Interrupt sources are globally masked. The processor
* is running in thread-privileged mode.
* - <b>Sleep</b>. This state is entered with the execution of the specific
* instruction @p <b>wfi</b>.
* - <b>S-Locked</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in thread-privileged mode.
* - <b>I-Locked</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in exception-privileged mode.
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
* not globally masked but only interrupts with higher priority can preempt
* the current handler. The processor is running in exception-privileged mode.
* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
* but it is not possible to switch to the I-Locked state because fast
* interrupts can preempt the kernel critical zone.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered to be in this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
* .
* @section ARMCM3_NOTES The ARM Cortex-M3 port notes
* The ARM Cortex-M3 port is organized as follow:
* - The @p main() function is invoked in thread-privileged mode.
* - Each thread has a private process stack, the system has a single main
* stack where all the interrupts and exceptions are processed.
* - Only the 4 MSb of the priority level are used, the 4 LSb are assumed
* to be zero.
* - The threads are started in thread-privileged mode with BASEPRI level
* 0x00 (disabled).
* - The kernel raises its BASEPRI level to @p CORTEX_BASEPRI_KERNEL in order
* to protect the kernel data structures.
* - Interrupt nesting and the other advanced NVIC features are supported.
* - The SVC instruction and vector, with parameter #0, is internally used
* for commanded context switching.<br>
* It is possible to share the SVC handler at the cost of slower context
* switching.
* - The PendSV vector is internally used for preemption context switching.
* .
* @ingroup ports
*/
/**
* @defgroup ARMCM3_CONF Configuration Options
* @brief ARM Cortex-M3 Configuration Options.
* @details The ARMCM3 port allows some architecture-specific configurations
* settings that can be specified externally, as example on the compiler
* command line:
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
* by an interrupt handler between the @p extctx and @p intctx
* structures.<br>
* In the current implementation this value is guaranteed to be zero so
* there is no need to modify this value unless changes are done at the
* interrupts handling code.
* - @p CORTEX_BASEPRI_USER, this is the @p BASEPRI value for the user threads.
* The default value is @p 0 (disabled).<br>
* Usually there is no need to change this value, please refer to the
* Cortex-M3 technical reference manual for a detailed description.
* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
* code.<br>
* Code running at higher priority levels must not invoke any OS API.<br>
* Usually there is no need to change this value, please refer to the
* Cortex-M3 technical reference manual for a detailed description.
* - @p ENABLE_WFI_IDLE, if set to @p 1 enables the use of the @p <b>wfi</b>
* instruction from within the idle loop. This is defaulted to 0 because
* it can create problems with some debuggers. Setting this option to 1
* reduces the system power requirements.
* .
* @ingroup ARMCM3
*/
/**
* @defgroup ARMCM3_CORE Core Port Implementation
* @brief ARM Cortex-M3 specific port code, structures and macros.
*
* @ingroup ARMCM3
*/
/**
* @defgroup ARMCM3_STARTUP Startup Support
* @brief ARM Cortex-M3 startup code support.
* @details ChibiOS/RT provides its own generic startup file for the ARM
* Cortex-M3 port.
* Of course it is not mandatory to use it but care should be taken about the
* startup phase details.
*
* <h2>Startup Process</h2>
* The startup process, as implemented, is the following:
* -# Interrupts are masked globally.
* -# The two stacks are initialized by assigning them the sizes defined in the
* linker script (usually named @p ch.ld). Stack areas are allocated from
* the highest RAM location downward.
* -# An early initialization routine @p hwinit0 is invoked, if the symbol is
* not defined then an empty default routine is executed (weak symbol).
* -# DATA and BSS segments are initialized.
* -# The CPU state is switched to Privileged and the PSP stack is used.
* -# A late initialization routine @p hwinit1 is invoked, if the symbol not
* defined then an empty default routine is executed (weak symbol).<br>
* This late initialization function is also the proper place for a
* @a bootloader, if your application requires one.
* -# The @p main() function is invoked with the parameters @p argc and @p argv
* set to zero.
* -# Should the @p main() function return a branch is performed to the weak
* symbol MainExitHandler. The default code is an endless empty loop.
* .
* <h2>Expected linker symbols</h2>
* The startup code starts at the symbol @p ResetHandler and expects the
* following symbols to be defined in the linker script:
* - @p __ram_end__ RAM end location +1.
* - @p __main_stack_size__ Exception stack size.
* - @p __process_stack_size__ Process stack size. This is the stack area used
* by the @p main() function.
* - @p _textdata address of the data segment source read only data.
* - @p _data data segment start location.
* - @p _edata data segment end location +1.
* - @p _bss_start BSS start location.
* - @p _bss_end BSS end location +1.
* .
* @ingroup ARMCM3
*/
/**
* @defgroup ARMCM3_NVIC NVIC Support
* @brief ARM Cortex-M3 NVIC support.
*
* @ingroup ARMCM3
*/

65
os/ports/GCC/ARMCMx/port.dox
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@ -22,24 +22,7 @@
* @details This port supports the ARMv6-M and ARMv7-M architectures (all the
* Cortex-Mx cores).
*
* @section ARMCMx_STATES Mapping of the System States in the ARM Cortex-Mx port
* This port supports two IRQ handling modes:
* - <b>IRQ disabling</b>. This is the simplest and most efficient way to
* implement kernel locks, this is done by globally disabling interrupts.
* This mode is available to both the ARMv6-M and ARMv7-M architectures.
* - <b>IRQ priority masking</b>. In this mode kernel locks are implemented by
* raising the priority mask to the @p CORTEX_BASEPRI_KERNEL level. Using
* priority masking it is possible to reserve one or more priority levels
* for use as fast interrupt handlers. This mode is slightly less efficient
* because the lock/unlock code requires two instructions instead of just
* one and is available to the ARMv7-M architecture only (Cortex-M3 and
* Cortex-M4). The advantage in this mode is the availability of very low
* latency priority levels unaffected by the RTOS activity.
* .
* The mapping of the @ref system_states changes depending on the chosen IRQ
* handling mode.
*
* @subsection ARMCMx_STATES_A System logical states in IRQ disabling mode
* @section ARMCMx_STATES_A System logical states in ARMv6-M
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
@ -62,7 +45,8 @@
* not globally masked but only interrupts with higher priority can preempt
* the current handler. The processor is running in exception-privileged
* mode.
* - <b>Serving Fast Interrupt</b>. This state is not implemented in this mode.
* - <b>Serving Fast Interrupt</b>. This state is not implemented in the
* ARMv6-M implementation.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
@ -70,7 +54,7 @@
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
*
* @subsection ARMCMx_STATES_B System logical states in IRQ priority masking mode
* @section ARMCMx_STATES_B System logical states in ARMv7-M
* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
* Cortex-M3 port:
* - <b>Init</b>. This state is represented by the startup code and the
@ -124,30 +108,27 @@
/**
* @defgroup ARMCMx_CONF Configuration Options
* @brief ARM Cortex-Mx Configuration Options.
* @details The ARMCM3 port allows some architecture-specific configurations
* settings that can be specified externally, as example on the compiler
* command line:
* @details The ARMCMx port allows some architecture-specific configurations
* settings that can be overridden externally. Usually there is no need to
* change the default values.
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
* by an interrupt handler between the @p extctx and @p intctx
* structures.<br>
* In the current implementation this value is guaranteed to be zero so
* there is no need to modify this value unless changes are done at the
* interrupts handling code.
* - @p CORTEX_BASEPRI_USER, this is the @p BASEPRI value for the user threads.
* The default value is @p 0 (disabled).<br>
* Usually there is no need to change this value, please refer to the
* Cortex-M3 technical reference manual for a detailed description.
* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
* code.<br>
* Code running at higher priority levels must not invoke any OS API.<br>
* Usually there is no need to change this value, please refer to the
* Cortex-M3 technical reference manual for a detailed description.
* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p 1 enables the use of the
* code. Code running at higher priority levels must not invoke any OS API.
* This setting is specific to the ARMv7-M architecture.
* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
* @p <b>wfi</b> instruction from within the idle loop. This is defaulted to
* 0 because it can create problems with some debuggers. Setting this option
* to 1 reduces the system power requirements.
* FALSE because it can create problems with some debuggers. Setting this
* option to TRUE reduces the system power requirements.
* .
* @ingroup ARMCM3
* @ingroup ARMCMx
*/
/**
@ -157,6 +138,20 @@
* @ingroup ARMCMx
*/
/**
* @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation
* @brief ARMv6-M specific port code, structures and macros.
*
* @ingroup ARMCMx_CORE
*/
/**
* @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation
* @brief ARMv7-M specific port code, structures and macros.
*
* @ingroup ARMCMx_CORE
*/
/**
* @defgroup ARMCMx_STARTUP Startup Support
* @brief ARM Cortex-Mx startup code support.

4
readme.txt
View File

@ -62,6 +62,10 @@
- FIX: Fixed missing memory recovery on thread reference release in
chRegNextThread() (bug 2971878).
- FIX: Fixed wrong thread state macro in STM32/spi_lld.c (bug 2968142).
- NEW: New unified ARM Cortex-Mx port, this port supports both the ARMv6M
and ARMv7-M architecture (Cortex-M0/M1/M3/M4 so far). The new port also
allow to easily add to new Cortex-M implementations by simply adding a
parameters file (cmparams.h).
- NEW: The port layer now can "capture" the implementation of individual
scheduler API functions in order to provide architecture-optimized
versions. This is done because further scheduler optimizations are

4
testhal/STM32/Makefile
View File

@ -60,7 +60,7 @@ CHIBIOS = ../..
include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
@ -102,7 +102,7 @@ TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM) \
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \

26
testhal/STM32/mcuconf.h
View File

@ -45,14 +45,14 @@
*/
#define USE_STM32_ADC1 TRUE
#define STM32_ADC1_DMA_PRIORITY 3
#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
#define STM32_ADC1_IRQ_PRIORITY 5
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
/*
* CAN driver system settings.
*/
#define USE_STM32_CAN1 TRUE
#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
#define STM32_CAN1_IRQ_PRIORITY 11
/*
* PWM driver system settings.
@ -61,10 +61,10 @@
#define USE_STM32_PWM2 FALSE
#define USE_STM32_PWM3 FALSE
#define USE_STM32_PWM4 FALSE
#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM1_IRQ_PRIORITY 7
#define STM32_PWM2_IRQ_PRIORITY 7
#define STM32_PWM3_IRQ_PRIORITY 7
#define STM32_PWM4_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
@ -76,12 +76,12 @@
#define USE_STM32_UART4 FALSE
#define USE_STM32_UART5 FALSE
#endif
#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART1_PRIORITY 12
#define STM32_USART2_PRIORITY 12
#define STM32_USART3_PRIORITY 12
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
#define STM32_UART4_PRIORITY 12
#define STM32_UART5_PRIORITY 12
#endif
/*
@ -91,6 +91,6 @@
#define USE_STM32_SPI2 TRUE
#define STM32_SPI1_DMA_PRIORITY 2
#define STM32_SPI2_DMA_PRIORITY 2
#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI1_IRQ_PRIORITY 10
#define STM32_SPI2_IRQ_PRIORITY 10
#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()