diff --git a/demos/MAX32/RT-MAX32625-MAX32625MBED/Makefile b/demos/MAX32/RT-MAX32625-MAX32625MBED/Makefile index c3fb7db87..02ffd796c 100644 --- a/demos/MAX32/RT-MAX32625-MAX32625MBED/Makefile +++ b/demos/MAX32/RT-MAX32625-MAX32625MBED/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). diff --git a/demos/MAX32/RT-MAX32625-MAX32625MBED/build/ch.elf b/demos/MAX32/RT-MAX32625-MAX32625MBED/build/ch.elf deleted file mode 100644 index 3084326db..000000000 Binary files a/demos/MAX32/RT-MAX32625-MAX32625MBED/build/ch.elf and /dev/null differ diff --git a/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/chconf.h b/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/chconf.h index 0f403b389..947580edb 100644 --- a/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/chconf.h +++ b/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/chconf.h @@ -72,7 +72,7 @@ * setting also defines the system tick time unit. */ #if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 +#define CH_CFG_ST_FREQUENCY 1000 #endif /** diff --git a/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/halconf.h b/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/halconf.h index bc22469ab..fa4533ebf 100644 --- a/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/halconf.h +++ b/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/halconf.h @@ -37,7 +37,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL FALSE +#define HAL_USE_PAL TRUE #endif /** diff --git a/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/mcuconf.h b/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/mcuconf.h index 4c12ebfc6..bd667d543 100644 --- a/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/mcuconf.h +++ b/demos/MAX32/RT-MAX32625-MAX32625MBED/cfg/mcuconf.h @@ -27,6 +27,7 @@ * HAL driver system settings. */ #define MAX32_NO_INIT FALSE +#define MAX32_SYS_SRC MAX32_SYS_SRC_SRO #define MAX32_CM4_DIV MAX32_CM4_DIV1 /* diff --git a/demos/MAX32/RT-MAX32625-MAX32625MBED/main.c b/demos/MAX32/RT-MAX32625-MAX32625MBED/main.c index 6259365c2..7f07fef33 100644 --- a/demos/MAX32/RT-MAX32625-MAX32625MBED/main.c +++ b/demos/MAX32/RT-MAX32625-MAX32625MBED/main.c @@ -29,8 +29,22 @@ static THD_FUNCTION(Thread1, arg) { (void)arg; chRegSetThreadName("blinker"); while (true) { - //palSetLine(LINE_LED_GREEN); + palSetLine(LINE_LED_RED); chThdSleepMilliseconds(50); + palSetLine(LINE_LED_GREEN); + chThdSleepMilliseconds(50); + palSetLine(LINE_LED_BLUE); + chThdSleepMilliseconds(50); + palSetLine(LINE_LED_ORANGE); + chThdSleepMilliseconds(200); + palClearLine(LINE_LED_RED); + chThdSleepMilliseconds(50); + palClearLine(LINE_LED_GREEN); + chThdSleepMilliseconds(50); + palClearLine(LINE_LED_BLUE); + chThdSleepMilliseconds(50); + palClearLine(LINE_LED_ORANGE); + chThdSleepMilliseconds(200); } } diff --git a/os/common/ext/ADI/MAX3262x/max32625.h b/os/common/ext/ADI/MAX3262x/max32625.h deleted file mode 100644 index 40e39c3f9..000000000 --- a/os/common/ext/ADI/MAX3262x/max32625.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef __MAX32625_H__ -#define __MAX32625_H__ - -#define MXC_UART_REV 1 - -/* To add here support for 626 and 620 */ -#if defined(MAX32625) -#include "MAX32625.h" -#else -#include "MAX32625.h" -#endif - -#endif /* __MAX3262x_H__ */ -#ifndef __MAX32625_H__ -#define __MAX32625_H__ - -#include "MAX32625/adc_regs.h" -#include "MAX32625/aes_regs.h" -#include "MAX32625/clkman_regs.h" -#include "MAX32625/crc_regs.h" -#include "MAX32625/flc_regs.h" -#include "MAX32625/gpio_regs.h" -#include "MAX32625/i2cm_regs.h" -#include "MAX32625/i2cs_regs.h" -#include "MAX32625/icc_regs.h" -#include "MAX32625/ioman_regs.h" -#include "MAX32625/maa_regs.h" -#include "MAX32625/max32625.h" -//#include "MAX32625/mxc_device.h" -#include "MAX32625/owm_regs.h" -#include "MAX32625/pmu_regs.h" -#include "MAX32625/prng_regs.h" -#include "MAX32625/pt_regs.h" -#include "MAX32625/pwrman_regs.h" -#include "MAX32625/pwrseq_regs.h" -#include "MAX32625/rtc_regs.h" -#include "MAX32625/spim_regs.h" -#include "MAX32625/spis_regs.h" -#include "MAX32625/spix_regs.h" -#include "MAX32625/sysman_regs.h" -#include "MAX32625/system_max32625.h" -#include "MAX32625/tmr_regs.h" -#include "MAX32625/tpu_regs.h" -#include "MAX32625/trim_regs.h" -#include "MAX32625/uart_regs.h" -#include "MAX32625/usb_regs.h" -#include "MAX32625/wdt2_regs.h" -#include "MAX32625/wdt_regs.h" - -#endif /* __MAX32625_H__ */ diff --git a/os/hal/boards/ADICUP360/board.c b/os/hal/boards/ADICUP360/board.c index 4b2fbb6df..65e55c785 100644 --- a/os/hal/boards/ADICUP360/board.c +++ b/os/hal/boards/ADICUP360/board.c @@ -35,7 +35,7 @@ /*===========================================================================*/ /** - * @brief Type of ADUCM36x GP port setup. + * @brief Type of ADUCM36x GPIO port setup. */ typedef struct { uint32_t con; @@ -54,7 +54,7 @@ typedef struct { } gp_config_t; /** - * @brief STM32 GPIO static initialization data. + * @brief ADUCM36x GPIO static initialization data. */ static const gp_config_t gp_default_config = { {VAL_GP0CON, VAL_GP0OEN, VAL_GP0PUL, VAL_GP0OCE}, diff --git a/os/hal/boards/ADICUP360/board.h b/os/hal/boards/ADICUP360/board.h index d0a685e37..a888bf528 100644 --- a/os/hal/boards/ADICUP360/board.h +++ b/os/hal/boards/ADICUP360/board.h @@ -79,7 +79,6 @@ #define GP2_6 6U #define GP2_7 7U - /* * IO lines assignments. */ diff --git a/os/hal/boards/ADI_MAX32625MBED/board.c b/os/hal/boards/ADI_MAX32625MBED/board.c index c13317691..716988eda 100644 --- a/os/hal/boards/ADI_MAX32625MBED/board.c +++ b/os/hal/boards/ADI_MAX32625MBED/board.c @@ -20,6 +20,7 @@ */ #include "hal.h" +#include "max32_gpio.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -33,10 +34,60 @@ /* Driver local variables and types. */ /*===========================================================================*/ +/** + * @brief Type of MAX32625 GPIO port setup. + */ +typedef struct { + uint32_t outmode; + uint32_t outval; + uint32_t funcsel; + uint32_t inmode; +} gpio_setup_t; + +/** + * @brief Type of MAX32625 GPIO initialization data. + */ +typedef struct { + gpio_setup_t GPIO0Data; + gpio_setup_t GPIO1Data; + gpio_setup_t GPIO2Data; + gpio_setup_t GPIO3Data; + gpio_setup_t GPIO4Data; +} gpio_config_t; + +/** + * @brief MAX32625 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { + {VAL_GPIO0_OUTMODE, VAL_GPIO0_OUTVAL, VAL_GPIO0_FUNCSEL, VAL_GPIO0_INMODE}, + {VAL_GPIO1_OUTMODE, VAL_GPIO1_OUTVAL, VAL_GPIO1_FUNCSEL, VAL_GPIO1_INMODE}, + {VAL_GPIO2_OUTMODE, VAL_GPIO2_OUTVAL, VAL_GPIO2_FUNCSEL, VAL_GPIO2_INMODE}, + {VAL_GPIO3_OUTMODE, VAL_GPIO3_OUTVAL, VAL_GPIO3_FUNCSEL, VAL_GPIO3_INMODE}, + {VAL_GPIO4_OUTMODE, VAL_GPIO4_OUTVAL, VAL_GPIO4_FUNCSEL, VAL_GPIO4_INMODE} +}; + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ +static void gpio_init(max32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OUT_MODE = config->outmode; + gpiop->OUT_VAL = config->outval; + gpiop->FUNC_SEL = config->funcsel; + gpiop->IN_MODE = config->inmode; +} + +static void max32_gpio_init(void) { + + /* Initializing all the defined GP ports.*/ + gpio_init(GPIO0, &gpio_default_config.GPIO0Data); + gpio_init(GPIO1, &gpio_default_config.GPIO1Data); + gpio_init(GPIO2, &gpio_default_config.GPIO2Data); + gpio_init(GPIO3, &gpio_default_config.GPIO3Data); + gpio_init(GPIO4, &gpio_default_config.GPIO4Data); +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -52,7 +103,7 @@ */ void __early_init(void) { - //stm32_gpio_init(); + max32_gpio_init(); max32_clock_init(); } diff --git a/os/hal/boards/ADI_MAX32625MBED/board.h b/os/hal/boards/ADI_MAX32625MBED/board.h index b5591c457..ced07aa4c 100644 --- a/os/hal/boards/ADI_MAX32625MBED/board.h +++ b/os/hal/boards/ADI_MAX32625MBED/board.h @@ -41,6 +41,74 @@ */ #define MAX32625 +/* + * IO pins assignments. + */ +#define GPIO0_0 0U +#define GPIO0_1 1U +#define GPIO0_2 2U +#define GPIO0_3 3U +#define GPIO0_4 4U +#define GPIO0_5 5U +#define GPIO0_6 6U +#define GPIO0_7 7U + +#define GPIO1_0 0U +#define GPIO1_1 1U +#define GPIO1_2 2U +#define GPIO1_3 3U +#define GPIO1_4 4U +#define GPIO1_5 5U +#define GPIO1_6 6U +#define GPIO1_7 7U + +#define GPIO2_0 0U +#define GPIO2_DAPLINK_RX 0U +#define GPIO2_1 1U +#define GPIO2_DAPLINK_TX 1U +#define GPIO2_2 2U +#define GPIO2_BUTTON2 2U +#define GPIO2_3 3U +#define GPIO2_BUTTON3 3U +#define GPIO2_4 4U +#define GPIO2_5 5U +#define GPIO2_6 6U +#define GPIO2_7 7U + +#define GPIO3_0 0U +#define GPIO3_LED_RED 0U +#define GPIO3_1 1U +#define GPIO3_LED_GREEN 0U +#define GPIO3_2 2U +#define GPIO3_LED_BLUE 0U +#define GPIO3_3 3U +#define GPIO3_LED_ORANGE 0U +#define GPIO3_4 4U +#define GPIO3_5 5U +#define GPIO3_6 6U +#define GPIO3_7 7U + +#define GPIO4_0 0U +#define GPIO4_1 1U +#define GPIO4_2 2U +#define GPIO4_3 3U +#define GPIO4_4 4U +#define GPIO4_5 5U +#define GPIO4_6 6U +#define GPIO4_7 7U + +/* + * IO lines assignments. + */ +#define LINE_DAPLINK_RX PAL_LINE(GPIO2, 0U) +#define LINE_DAPLINK_TX PAL_LINE(GPIO2, 1U) +#define LINE_BUTTON2 PAL_LINE(GPIO2, 2U) +#define LINE_BUTTON3 PAL_LINE(GPIO2, 3U) +#define LINE_LED_RED PAL_LINE(GPIO3, 0U) +#define LINE_LED_GREEN PAL_LINE(GPIO3, 1U) +#define LINE_LED_BLUE PAL_LINE(GPIO3, 2U) +#define LINE_LED_ORANGE PAL_LINE(GPIO3, 3U) + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -57,6 +125,261 @@ /* Driver macros. */ /*===========================================================================*/ +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the MAX32625 Reference Manual for details. + */ +#define PIN_OMODE_HIGHZ_PULLUP(n) (0U << (4 * n)) +#define PIN_OMODE_OPENDRAIN(n) (1U << (4 * n)) +#define PIN_OMODE_OPENDRAIN_PULLUP(n) (2U << (4 * n)) +#define PIN_OMODE_NORMAL_HIGHZ(n) (4U << (4 * n)) +#define PIN_OMODE_NORMAL_DRIVE(n) (5U << (4 * n)) +#define PIN_OMODE_SLOW_HIGHZ(n) (6U << (4 * n)) +#define PIN_OMODE_SLOW_DRIVE(n) (7U << (4 * n)) +#define PIN_OMODE_FAST_HIGHZ(n) (8U << (4 * n)) +#define PIN_OMODE_FAST_DRIVE(n) (9U << (4 * n)) +#define PIN_OMODE_HIGHZ_PULLDOWN(n) (10U << (4 * n)) +#define PIN_OMODE_OPENSOURCE(n) (11U << (4 * n)) +#define PIN_OMODE_OPENSOURCE_PULLDOWN(n) (12U << (4 * n)) +#define PIN_OMODE_DISABLED(n) (15U << (4 * n)) + +#define PIN_OV_LOW(n) (0U << (n)) +#define PIN_OV_HIGH(n) (1U << (n)) + +#define PIN_FUNC_GPIO(n) (0U << (4 * n)) +#define PIN_FUNC_PULSE(n) (1U << (4 * n)) +#define PIN_FUNC_TIMER(n) (2U << (4 * n)) + +#define PIN_IMODE_NORMAL_INPUT(n) (0U << (4 * n)) +#define PIN_IMODE_INVERTED_INPUT(n) (1U << (4 * n)) +#define PIN_IMODE_ALWAYS_LOW(n) (2U << (4 * n)) +#define PIN_IMODE_ALWAYS_HIGH(n) (3U << (4 * n)) + +/* + * GPIO0 setup: + * + * GPIO0.0 - PIN0 High-Z, input disabled. + * GPIO0.1 - PIN1 High-Z, input disabled. + * GPIO0.2 - PIN2 High-Z, input disabled. + * GPIO0.3 - PIN3 High-Z, input disabled. + * GPIO0.4 - PIN4 High-Z, input disabled. + * GPIO0.5 - PIN5 High-Z, input disabled. + * GPIO0.6 - PIN6 High-Z, input disabled. + * GPIO0.7 - PIN6 High-Z, input disabled. + */ +#define VAL_GPIO0_OUTMODE (PIN_OMODE_DISABLED(GPIO0_0) | \ + PIN_OMODE_DISABLED(GPIO0_1) | \ + PIN_OMODE_DISABLED(GPIO0_2) | \ + PIN_OMODE_DISABLED(GPIO0_3) | \ + PIN_OMODE_DISABLED(GPIO0_4) | \ + PIN_OMODE_DISABLED(GPIO0_5) | \ + PIN_OMODE_DISABLED(GPIO0_6) | \ + PIN_OMODE_DISABLED(GPIO0_7)) +#define VAL_GPIO0_OUTVAL (PIN_OV_LOW(GPIO0_0) | \ + PIN_OV_LOW(GPIO0_1) | \ + PIN_OV_LOW(GPIO0_2) | \ + PIN_OV_LOW(GPIO0_3) | \ + PIN_OV_LOW(GPIO0_4) | \ + PIN_OV_LOW(GPIO0_5) | \ + PIN_OV_LOW(GPIO0_6) | \ + PIN_OV_LOW(GPIO0_7)) +#define VAL_GPIO0_FUNCSEL (PIN_FUNC_GPIO(GPIO0_0) | \ + PIN_FUNC_GPIO(GPIO0_1) | \ + PIN_FUNC_GPIO(GPIO0_2) | \ + PIN_FUNC_GPIO(GPIO0_3) | \ + PIN_FUNC_GPIO(GPIO0_4) | \ + PIN_FUNC_GPIO(GPIO0_5) | \ + PIN_FUNC_GPIO(GPIO0_6) | \ + PIN_FUNC_GPIO(GPIO0_7)) +#define VAL_GPIO0_INMODE (PIN_IMODE_NORMAL_INPUT(GPIO0_0) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_1) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_2) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_3) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_4) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_5) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_6) | \ + PIN_IMODE_NORMAL_INPUT(GPIO0_7)) + +/* + * GPIO1 setup: + * + * GPIO1.0 - PIN0 High-Z, input disabled. + * GPIO1.1 - PIN1 High-Z, input disabled. + * GPIO1.2 - PIN2 High-Z, input disabled. + * GPIO1.3 - PIN3 High-Z, input disabled. + * GPIO1.4 - PIN4 High-Z, input disabled. + * GPIO1.5 - PIN5 High-Z, input disabled. + * GPIO1.6 - PIN6 High-Z, input disabled. + * GPIO1.7 - PIN6 High-Z, input disabled. + */ +#define VAL_GPIO1_OUTMODE (PIN_OMODE_DISABLED(GPIO1_0) | \ + PIN_OMODE_DISABLED(GPIO1_1) | \ + PIN_OMODE_DISABLED(GPIO1_2) | \ + PIN_OMODE_DISABLED(GPIO1_3) | \ + PIN_OMODE_DISABLED(GPIO1_4) | \ + PIN_OMODE_DISABLED(GPIO1_5) | \ + PIN_OMODE_DISABLED(GPIO1_6) | \ + PIN_OMODE_DISABLED(GPIO1_7)) +#define VAL_GPIO1_OUTVAL (PIN_OV_LOW(GPIO1_0) | \ + PIN_OV_LOW(GPIO1_1) | \ + PIN_OV_LOW(GPIO1_2) | \ + PIN_OV_LOW(GPIO1_3) | \ + PIN_OV_LOW(GPIO1_4) | \ + PIN_OV_LOW(GPIO1_5) | \ + PIN_OV_LOW(GPIO1_6) | \ + PIN_OV_LOW(GPIO1_7)) +#define VAL_GPIO1_FUNCSEL (PIN_FUNC_GPIO(GPIO1_0) | \ + PIN_FUNC_GPIO(GPIO1_1) | \ + PIN_FUNC_GPIO(GPIO1_2) | \ + PIN_FUNC_GPIO(GPIO1_3) | \ + PIN_FUNC_GPIO(GPIO1_4) | \ + PIN_FUNC_GPIO(GPIO1_5) | \ + PIN_FUNC_GPIO(GPIO1_6) | \ + PIN_FUNC_GPIO(GPIO1_7)) +#define VAL_GPIO1_INMODE (PIN_IMODE_NORMAL_INPUT(GPIO1_0) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_1) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_2) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_3) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_4) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_5) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_6) | \ + PIN_IMODE_NORMAL_INPUT(GPIO1_7)) + +/* + * GPIO2 setup: + * + * GPIO2.0 - DAPLINK_RX High-Z, input disabled. + * GPIO2.1 - DAPLINK_TX High-Z, input disabled. + * GPIO2.2 - BUTTON2 Normal input. + * GPIO2.3 - BUTTON3 Normal input. + * GPIO2.4 - PIN4 High-Z, input disabled. + * GPIO2.5 - PIN5 High-Z, input disabled. + * GPIO2.6 - PIN6 High-Z, input disabled. + * GPIO2.7 - PIN6 High-Z, input disabled. + */ +#define VAL_GPIO2_OUTMODE (PIN_OMODE_DISABLED(GPIO2_0) | \ + PIN_OMODE_DISABLED(GPIO2_1) | \ + PIN_OMODE_NORMAL_HIGHZ(GPIO2_2) | \ + PIN_OMODE_NORMAL_HIGHZ(GPIO2_3) | \ + PIN_OMODE_DISABLED(GPIO2_4) | \ + PIN_OMODE_DISABLED(GPIO2_5) | \ + PIN_OMODE_DISABLED(GPIO2_6) | \ + PIN_OMODE_DISABLED(GPIO2_7)) +#define VAL_GPIO2_OUTVAL (PIN_OV_LOW(GPIO2_0) | \ + PIN_OV_LOW(GPIO2_1) | \ + PIN_OV_LOW(GPIO2_2) | \ + PIN_OV_LOW(GPIO2_3) | \ + PIN_OV_LOW(GPIO2_4) | \ + PIN_OV_LOW(GPIO2_5) | \ + PIN_OV_LOW(GPIO2_6) | \ + PIN_OV_LOW(GPIO2_7)) +#define VAL_GPIO2_FUNCSEL (PIN_FUNC_GPIO(GPIO2_0) | \ + PIN_FUNC_GPIO(GPIO2_1) | \ + PIN_FUNC_GPIO(GPIO2_2) | \ + PIN_FUNC_GPIO(GPIO2_3) | \ + PIN_FUNC_GPIO(GPIO2_4) | \ + PIN_FUNC_GPIO(GPIO2_5) | \ + PIN_FUNC_GPIO(GPIO2_6) | \ + PIN_FUNC_GPIO(GPIO2_7)) +#define VAL_GPIO2_INMODE (PIN_IMODE_NORMAL_INPUT(GPIO2_0) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_1) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_2) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_3) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_4) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_5) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_6) | \ + PIN_IMODE_NORMAL_INPUT(GPIO2_7)) + +/* + * GPIO3 setup: + * + * GPIO3.0 - LED_RED Fast output, high state. + * GPIO3.1 - LED_GREEN Fast output, high state. + * GPIO3.2 - LED_BLUE Fast output, high state. + * GPIO3.3 - LED_ORANGE Fast output, high state. + * GPIO3.4 - PIN4 High-Z, input disabled. + * GPIO3.5 - PIN5 High-Z, input disabled. + * GPIO3.6 - PIN6 High-Z, input disabled. + * GPIO3.7 - PIN6 High-Z, input disabled. + */ +#define VAL_GPIO3_OUTMODE (PIN_OMODE_FAST_DRIVE(GPIO3_0) | \ + PIN_OMODE_FAST_DRIVE(GPIO3_1) | \ + PIN_OMODE_FAST_DRIVE(GPIO3_2) | \ + PIN_OMODE_FAST_DRIVE(GPIO3_3) | \ + PIN_OMODE_DISABLED(GPIO3_4) | \ + PIN_OMODE_DISABLED(GPIO3_5) | \ + PIN_OMODE_DISABLED(GPIO3_6) | \ + PIN_OMODE_DISABLED(GPIO3_7)) +#define VAL_GPIO3_OUTVAL (PIN_OV_HIGH(GPIO3_0) | \ + PIN_OV_HIGH(GPIO3_1) | \ + PIN_OV_HIGH(GPIO3_2) | \ + PIN_OV_HIGH(GPIO3_3) | \ + PIN_OV_LOW(GPIO3_4) | \ + PIN_OV_LOW(GPIO3_5) | \ + PIN_OV_LOW(GPIO3_6) | \ + PIN_OV_LOW(GPIO3_7)) +#define VAL_GPIO3_FUNCSEL (PIN_FUNC_GPIO(GPIO3_0) | \ + PIN_FUNC_GPIO(GPIO3_1) | \ + PIN_FUNC_GPIO(GPIO3_2) | \ + PIN_FUNC_GPIO(GPIO3_3) | \ + PIN_FUNC_GPIO(GPIO3_4) | \ + PIN_FUNC_GPIO(GPIO3_5) | \ + PIN_FUNC_GPIO(GPIO3_6) | \ + PIN_FUNC_GPIO(GPIO3_7)) +#define VAL_GPIO3_INMODE (PIN_IMODE_NORMAL_INPUT(GPIO3_0) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_1) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_2) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_3) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_4) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_5) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_6) | \ + PIN_IMODE_NORMAL_INPUT(GPIO3_7)) + +/* + * GPIO4 setup: + * + * GPIO4.0 - PIN0 High-Z, input disabled. + * GPIO4.1 - PIN1 High-Z, input disabled. + * GPIO4.2 - PIN2 High-Z, input disabled. + * GPIO4.3 - PIN3 High-Z, input disabled. + * GPIO4.4 - PIN4 High-Z, input disabled. + * GPIO4.5 - PIN5 High-Z, input disabled. + * GPIO4.6 - PIN6 High-Z, input disabled. + * GPIO4.7 - PIN6 High-Z, input disabled. + */ +#define VAL_GPIO4_OUTMODE (PIN_OMODE_DISABLED(GPIO4_0) | \ + PIN_OMODE_DISABLED(GPIO4_1) | \ + PIN_OMODE_DISABLED(GPIO4_2) | \ + PIN_OMODE_DISABLED(GPIO4_3) | \ + PIN_OMODE_DISABLED(GPIO4_4) | \ + PIN_OMODE_DISABLED(GPIO4_5) | \ + PIN_OMODE_DISABLED(GPIO4_6) | \ + PIN_OMODE_DISABLED(GPIO4_7)) +#define VAL_GPIO4_OUTVAL (PIN_OV_LOW(GPIO4_0) | \ + PIN_OV_LOW(GPIO4_1) | \ + PIN_OV_LOW(GPIO4_2) | \ + PIN_OV_LOW(GPIO4_3) | \ + PIN_OV_LOW(GPIO4_4) | \ + PIN_OV_LOW(GPIO4_5) | \ + PIN_OV_LOW(GPIO4_6) | \ + PIN_OV_LOW(GPIO4_7)) +#define VAL_GPIO4_FUNCSEL (PIN_FUNC_GPIO(GPIO4_0) | \ + PIN_FUNC_GPIO(GPIO4_1) | \ + PIN_FUNC_GPIO(GPIO4_2) | \ + PIN_FUNC_GPIO(GPIO4_3) | \ + PIN_FUNC_GPIO(GPIO4_4) | \ + PIN_FUNC_GPIO(GPIO4_5) | \ + PIN_FUNC_GPIO(GPIO4_6) | \ + PIN_FUNC_GPIO(GPIO4_7)) +#define VAL_GPIO4_INMODE (PIN_IMODE_NORMAL_INPUT(GPIO4_0) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_1) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_2) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_3) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_4) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_5) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_6) | \ + PIN_IMODE_NORMAL_INPUT(GPIO4_7)) /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/MAX32/MAX32625/hal_lld.c b/os/hal/ports/MAX32/MAX32625/hal_lld.c index 092bc342a..be3a333a9 100644 --- a/os/hal/ports/MAX32/MAX32625/hal_lld.c +++ b/os/hal/ports/MAX32/MAX32625/hal_lld.c @@ -80,7 +80,14 @@ void hal_lld_init(void) { void max32_clock_init(void) { #if !MAX32_NO_INIT + + /* Changing the clock source. */ + MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT; + MXC_CLKMAN->clk_ctrl |= MAX32_SYS_SRC; + + /* Applying the appropriate divider for the main core. */ MXC_CLKMAN->sys_clk_ctrl_0_cm4 = MAX32_CM4_DIV; + #endif /* !MAX32_NO_INIT */ } /** @} */ diff --git a/os/hal/ports/MAX32/MAX32625/hal_lld.h b/os/hal/ports/MAX32/MAX32625/hal_lld.h index 9bc51fce2..cef39d5c6 100644 --- a/os/hal/ports/MAX32/MAX32625/hal_lld.h +++ b/os/hal/ports/MAX32/MAX32625/hal_lld.h @@ -62,6 +62,14 @@ #define MAX32_RTC 32768 /**< Real Time Clock. */ /** @} */ +/** + * @name CLKMAN_CLK_CTRL System Source bit definition + * @{ + */ +#define MAX32_SYS_SRC_SRO_DIV2 (0 << 0) /**< The source is SRO divided by 2. */ +#define MAX32_SYS_SRC_SRO (1 << 0) /**< The source is SRO. */ +/** @} */ + /** * @name CLKMAN_SYS_CLK_CTRL_0_CM4 bit definition * @{ @@ -92,10 +100,17 @@ #define MAX32_NO_INIT FALSE #endif +/** + * @brief System clock source. + */ +#if !defined(MAX32_SYS_SRC) || defined(__DOXYGEN__) +#define MAX32_SYS_SRC MAX32_SYS_SRC_SRO +#endif + /** * @brief Main Core clock divider. */ -#if !defined(MAX32_CM4_DIV1) || defined(__DOXYGEN__) +#if !defined(MAX32_CM4_DIV) || defined(__DOXYGEN__) #define MAX32_CM4_DIV MAX32_CM4_DIV1 #endif /** @} */ @@ -112,27 +127,38 @@ #error "Using a wrong mcuconf.h file, MAX32625_MCUCONF not defined" #endif +/** + * @brief System clock frequency. + */ +#if (MAX32_SYS_SRC == MAX32_SYS_SRC_SRO) || defined(__DOXYGEN__) +#define MAX32_SYSCLK (MAX32_SRO / 1) +#elif MAX32_SYS_SRC == MAX32_SYS_SRC_SRO_DIV2 +#define MAX32_SYSCLK (MAX32_SRO / 2) +#else +#error "invalid clock source value specified" +#endif + /** * @brief Main core frequency. */ #if (MAX32_CM4_DIV == MAX32_CM4_DIV1) || defined(__DOXYGEN__) -#define MAX32_SYSCLK (MAX32_SRO / 1) +#define MAX32_CM4CLK (MAX32_SYSCLK / 1) #elif MAX32_CM4_DIV == MAX32_CM4_DIV2 -#define MAX32_SYSCLK (MAX32_SRO / 2) +#define MAX32_CM4CLK (MAX32_SYSCLK / 2) #elif MAX32_CM4_DIV == MAX32_CM4_DIV4 -#define MAX32_SYSCLK (MAX32_SRO / 4) +#define MAX32_CM4CLK (MAX32_SYSCLK / 4) #elif MAX32_CM4_DIV == MAX32_CM4_DIV8 -#define MAX32_SYSCLK (MAX32_SRO / 8) +#define MAX32_CM4CLK (MAX32_SYSCLK / 8) #elif MAX32_CM4_DIV == MAX32_CM4_DIV16 -#define MAX32_SYSCLK (MAX32_SRO / 16) +#define MAX32_CM4CLK (MAX32_SYSCLK / 16) #elif MAX32_CM4_DIV == MAX32_CM4_DIV32 -#define MAX32_SYSCLK (MAX32_SRO / 32) +#define MAX32_CM4CLK (MAX32_SYSCLK / 32) #elif MAX32_CM4_DIV == MAX32_CM4_DIV64 -#define MAX32_SYSCLK (MAX32_SRO / 64) +#define MAX32_CM4CLK (MAX32_SYSCLK / 64) #elif MAX32_CM4_DIV == MAX32_CM4_DIV128 -#define MAX32_SYSCLK (MAX32_SRO / 128) +#define MAX32_CM4CLK (MAX32_SYSCLK / 128) #elif MAX32_CM4_DIV == MAX32_CM4_DIV256 -#define MAX32_SYSCLK (MAX32_SRO / 256) +#define MAX32_CM4CLK (MAX32_SYSCLK / 256) #else #error "invalid MAX32_CM4_DIV value specified" #endif diff --git a/os/hal/ports/MAX32/MAX32625/hal_pal_lld.c b/os/hal/ports/MAX32/MAX32625/hal_pal_lld.c new file mode 100644 index 000000000..4434c2137 --- /dev/null +++ b/os/hal/ports/MAX32/MAX32625/hal_pal_lld.c @@ -0,0 +1,142 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MAX32625/hal_pal_lld.c + * @brief MAX32625 PAL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief PAL driver initialization. + * + * @notapi + */ +void _pal_lld_init(void) { + +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + uint32_t omode = (mode & PAL_MAX32_OMODE_MASK) >> PAL_MAX32_OMODE_OFF; + uint32_t funcsel = (mode & PAL_MAX32_FUNC_MASK) >> PAL_MAX32_FUNC_OFF; + uint32_t imode = (mode & PAL_MAX32_IMODE_MASK) >> PAL_MAX32_IMODE_OFF; + uint32_t bit = 0; + while (true) { + if ((mask & 1) != 0) { + uint32_t m1, m2; + /* Mask for bitfields large four bits. */ + m1 = 0x0FU << (bit * 4); + + /* Mask for bitfields large two bit. */ + m2 = 0x03U << (bit * 2); + + port->OUT_MODE = (port->OUT_MODE & ~m1) | omode; + port->FUNC_SEL = (port->FUNC_SEL & ~m1) | funcsel; + port->IN_MODE = (port->IN_MODE & ~m2) | imode; + + } + mask >>= 1; + + /* Mask is over. End the loop. */ + + if (!mask) + return; + omode <<= 4; + funcsel <<= 4; + imode <<= 2; + bit++; + } +} + + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented with a read modify write. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +void pal_lld_setport(ioportid_t port, uint32_t bits) { + uint32_t val = pal_lld_readlatch(port); + val |= bits; + pal_lld_writeport(port, val); +} + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented with a read modify write. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +void pal_lld_clearport(ioportid_t port, uint32_t bits) { + uint32_t val = pal_lld_readlatch(port); + val &= ~bits; + pal_lld_writeport(port, val); +} +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/ports/MAX32/MAX32625/hal_pal_lld.h b/os/hal/ports/MAX32/MAX32625/hal_pal_lld.h new file mode 100644 index 000000000..c04860756 --- /dev/null +++ b/os/hal/ports/MAX32/MAX32625/hal_pal_lld.h @@ -0,0 +1,386 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file MAX32625/hal_pal_lld.h + * @brief MAX32625 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#include "max32_gpio.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* IRQ priority checks.*/ +#if PAL_USE_CALLBACKS || PAL_USE_WAIT +#error "External interrupt still unsupported on this platform." +#endif + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/* Specifies palInit() without parameter, required until all platforms will + be updated to the new style.*/ +#define PAL_NEW_INIT + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name MAX32-specific I/O mode flags + * @{ + */ +#define PAL_MAX32_OMODE_OFF 0U +#define PAL_MAX32_OMODE_MASK (0xFU << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_HIGHZ_PULLUP (0x0U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_OPENDRAIN (0x1U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_OPENDRAIN_PULLUP (0x2U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_NORMAL_HIGHZ (0x4U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_NORMAL_DRIVE (0x5U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_SLOW_HIGHZ (0x6U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_SLOW_DRIVE (0x7U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_FAST_HIGHZ (0x8U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_FAST_DRIVE (0x9U << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_HIGHZ_PULLDOWN (0xAU << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_OPENSOURCE (0xBU << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_OPENSOURCE_PULLDOWN (0xCU << PAL_MAX32_OMODE_OFF) +#define PAL_MAX32_OMODE_DISABLED (0xFU << PAL_MAX32_OMODE_OFF) + +#define PAL_MAX32_FUNC_OFF 4U +#define PAL_MAX32_FUNC_MASK (0xFU << PAL_MAX32_FUNC_OFF) +#define PAL_MAX32_FUNC_GPIO (0x0U << PAL_MAX32_FUNC_OFF) +#define PAL_MAX32_FUNC_PULSE (0x1U << PAL_MAX32_FUNC_OFF) +#define PAL_MAX32_FUNC_TIMER (0x2U << PAL_MAX32_FUNC_OFF) + +#define PAL_MAX32_IMODE_OFF 8U +#define PAL_MAX32_IMODE_MASK (0x3U << PAL_MAX32_IMODE_OFF) +#define PAL_MAX32_IMODE_NORMAL_INPUT (0x0U << PAL_MAX32_IMODE_OFF) +#define PAL_MAX32_IMODE_INVERTED_INPUT (0x1U << PAL_MAX32_IMODE_OFF) +#define PAL_MAX32_IMODE_ALWAYS_LOW (0x2U << PAL_MAX32_IMODE_OFF) +#define PAL_MAX32_IMODE_ALWAYS_HIGH (0x3U << PAL_MAX32_IMODE_OFF) + + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief Implemented as input with pull-up. + */ +#define PAL_MODE_RESET (PAL_MAX32_OMODE_DISABLED |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Implemented as High-Z. + */ +#define PAL_MODE_UNCONNECTED (PAL_MAX32_OMODE_DISABLED |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Regular input floating. + */ +#define PAL_MODE_INPUT (PAL_MAX32_OMODE_NORMAL_HIGHZ |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_MAX32_OMODE_HIGHZ_PULLUP |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Not available: High-Z. + * @note Input floating here could be misleading. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_MAX32_OMODE_HIGHZ_PULLDOWN |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Not available: High-Z. + * @note Input floating here could be misleading. + */ +#define PAL_MODE_INPUT_ANALOG (PAL_MAX32_OMODE_NORMAL_HIGHZ |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_MAX32_OMODE_NORMAL_DRIVE |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) + +/** + * @brief Not available: High-Z. + * @note Standard output could create short-circuit. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_MAX32_OMODE_OPENDRAIN |\ + PAL_MAX32_FUNC_GPIO |\ + PAL_MAX32_IMODE_NORMAL_INPUT) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad << 16U))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((max32_gpio_t *)(((uint32_t)(line)) & 0xFFF0FFFFU)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)(((uint32_t)(line) & 0x000F0000)) >> 16U) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief Type of digital I/O port sized unsigned integer. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Type of digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Type of a port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef max32_gpio_t * ioportid_t; + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the MAX32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port 0 identifier. + */ +#define IOPORT0 GPIO0 + +/** + * @brief GPIO port 1 identifier. + */ +#define IOPORT1 GPIO1 + +/** + * @brief GPIO port 2 identifier. + */ +#define IOPORT2 GPIO2 + +/** + * @brief GPIO port 3 identifier. + */ +#define IOPORT3 GPIO3 + +/** + * @brief GPIO port 4 identifier. + */ +#define IOPORT4 GPIO4 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init() _pal_lld_init() + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIN register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((ioportmask_t)((port)->IN_VAL)) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPOUT register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((ioportmask_t)((port)->OUT_VAL)) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPOUT register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->OUT_VAL = (uint32_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPOUT register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) { \ + uint8_t w = ((uint8_t)(bits) & (uint8_t)(mask)) << (offset); \ + (port)->OUT_VAL = w; \ +} + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(void); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); + void pal_lld_setport(ioportid_t port, uint32_t bits); + void pal_lld_clearport(ioportid_t port, uint32_t bits); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/MAX32/MAX32625/hal_st_lld.c b/os/hal/ports/MAX32/MAX32625/hal_st_lld.c index eea3c4f9a..743f85f43 100644 --- a/os/hal/ports/MAX32/MAX32625/hal_st_lld.c +++ b/os/hal/ports/MAX32/MAX32625/hal_st_lld.c @@ -32,7 +32,7 @@ #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC -#define SYSTICK_CK MAX32_SYSCLK +#define SYSTICK_CK MAX32_CM4CLK #if SYSTICK_CK % OSAL_ST_FREQUENCY != 0 #error "the selected ST frequency is not obtainable because integer rounding" diff --git a/os/hal/ports/MAX32/MAX32625/max32_gpio.h b/os/hal/ports/MAX32/MAX32625/max32_gpio.h new file mode 100644 index 000000000..ea5cfdf83 --- /dev/null +++ b/os/hal/ports/MAX32/MAX32625/max32_gpio.h @@ -0,0 +1,103 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv2/max32_gpio.h + * @brief MAX32 GPIO units common header. + * @note This file requires definitions from the ST MAX32 header file. + * + * @addtogroup MAX32_GPIOv2 + * @{ + */ + +#ifndef MAX32_GPIO_H +#define MAX32_GPIO_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define GPIO0_BASE (MXC_BASE_GPIO + \ + MXC_R_GPIO_OFFS_RST_MODE_P0) +#define GPIO1_BASE (MXC_BASE_GPIO + \ + MXC_R_GPIO_OFFS_RST_MODE_P1) +#define GPIO2_BASE (MXC_BASE_GPIO + \ + MXC_R_GPIO_OFFS_RST_MODE_P2) +#define GPIO3_BASE (MXC_BASE_GPIO + \ + MXC_R_GPIO_OFFS_RST_MODE_P3) +#define GPIO4_BASE (MXC_BASE_GPIO + \ + MXC_R_GPIO_OFFS_RST_MODE_P4) +/** + * @name GPIO ports definitions + * @{ + */ +#define GPIO0 ((max32_gpio_t *)GPIO0_BASE) +#define GPIO1 ((max32_gpio_t *)GPIO1_BASE) +#define GPIO2 ((max32_gpio_t *)GPIO2_BASE) +#define GPIO3 ((max32_gpio_t *)GPIO3_BASE) +#define GPIO4 ((max32_gpio_t *)GPIO4_BASE) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief MAX32 GPIO registers block. + */ +typedef struct { + + volatile uint32_t RST; + volatile uint32_t RESERVED0[15]; + volatile uint32_t FREE; + volatile uint32_t RESERVED1[15]; + volatile uint32_t OUT_MODE; + volatile uint32_t RESERVED2[15]; + volatile uint32_t OUT_VAL; + volatile uint32_t RESERVED3[15]; + volatile uint32_t FUNC_SEL; + volatile uint32_t RESERVED4[15]; + volatile uint32_t IN_MODE; + volatile uint32_t RESERVED5[15]; + volatile uint32_t IN_VAL; + volatile uint32_t RESERVED6[15]; + volatile uint32_t INTMODE; + volatile uint32_t RESERVED7[15]; + volatile uint32_t INTFL; + volatile uint32_t RESERVED8[15]; + volatile uint32_t INTEN; + volatile uint32_t RESERVED9[15]; +} max32_gpio_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* MAX32_GPIO_H */ + +/** @} */ diff --git a/os/hal/ports/MAX32/MAX32625/platform.mk b/os/hal/ports/MAX32/MAX32625/platform.mk index 289f71230..ce48901d0 100644 --- a/os/hal/ports/MAX32/MAX32625/platform.mk +++ b/os/hal/ports/MAX32/MAX32625/platform.mk @@ -1,6 +1,7 @@ # Required platform files. PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/MAX32/MAX32625/hal_lld.c \ + $(CHIBIOS)/os/hal/ports/MAX32/MAX32625/hal_pal_lld.c \ $(CHIBIOS)/os/hal/ports/MAX32/MAX32625/hal_st_lld.c \ $(CHIBIOS)/os/hal/ports/MAX32/MAX32625/max32_isr.c